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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-02 22:42:53 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-04-05 13:16:22 +0000 |
| commit | e24f97c081f3e134362081913793d5adb90eddd5 (patch) | |
| tree | 0d1836ad9473b51ecca07dc2465a736201b08a8a /src/northbridge | |
| parent | 83e319d6f5b4802fdc862f4bcbe830ccb9e4dfa6 (diff) | |
| download | coreboot-e24f97c081f3e134362081913793d5adb90eddd5.tar.xz | |
nb/intel/ironlake: Drop `pci_mmio_size`
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/ironlake/chip.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/ironlake/raminit.c | 19 |
2 files changed, 1 insertions, 23 deletions
diff --git a/src/northbridge/intel/ironlake/chip.h b/src/northbridge/intel/ironlake/chip.h index b2976bced5..ab589ea221 100644 --- a/src/northbridge/intel/ironlake/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -34,11 +34,6 @@ struct northbridge_intel_ironlake_config { u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; - - /* - * Maximum PCI mmio size in MiB. - */ - u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f073ddae89..34e56571ca 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1273,23 +1273,6 @@ static void program_board_delay(struct raminfo *info) } #define DEFAULT_PCI_MMIO_SIZE 2048 -#define HOST_BRIDGE PCI_DEVFN(0, 0) - -static unsigned int get_mmio_size(void) -{ - const struct device *dev; - const struct northbridge_intel_ironlake_config *cfg = NULL; - - dev = pcidev_path_on_root(HOST_BRIDGE); - if (dev) - cfg = dev->chip_info; - - /* If this is zero, it just means devicetree.cb didn't set it */ - if (!cfg || cfg->pci_mmio_size == 0) - return DEFAULT_PCI_MMIO_SIZE; - else - return cfg->pci_mmio_size; -} static void program_total_memory_map(struct raminfo *info) { @@ -1323,7 +1306,7 @@ static void program_total_memory_map(struct raminfo *info) uma_size_gtt = uma_sizes_gtt[(t >> 8) & 0xF]; } - mmio_size = get_mmio_size(); + mmio_size = DEFAULT_PCI_MMIO_SIZE; tom = info->total_memory_mb; if (tom == 4096) |