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| author | Marc Jones <marc.jones@amd.com> | 2008-04-22 23:27:53 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2008-04-22 23:27:53 +0000 |
| commit | f0174b5a9c976401797d241c61b4fdf0f425cc6f (patch) | |
| tree | d8241d6f3843f4f693a4d19170efa7c1d79418c7 /src/northbridge | |
| parent | 8127dc41d1fde1118cdbe3bf6b592312b5b85c02 (diff) | |
| download | coreboot-f0174b5a9c976401797d241c61b4fdf0f425cc6f.tar.xz | |
Find matching settings for each CPUs FID, VID, and P-state registers and initialize them.
Supports single and split plane systems. Set P0 on all cores for best performance.
All APs will be in hlt(C1).
The platform warm rest logic has been updated to alway reset for HT and FID/VID setup. It is not optional anymore.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdht/AsPsDefs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 62b7edba6d..dfc6821ed9 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -157,7 +157,10 @@ #define CPTC1 0xd8 /* Clock Power/Timing Control1 Register*/ #define VSRAMP_SLAM_MASK 0xffffff88 /* MaskOff [VSRampTime]&[VSSlamTime] */ #define VSRAMP_SLAM_VALUE 0x16 /* [VSRampTime]=001b&[VSSlamTime]=110b */ +#define VSRAMP_MASK 0xffffff8f /* MaskOff [VSRampTime] */ +#define VSRAMP_VALUE 0x10 /* [VSRampTime]=001b */ #define VS_RAMP_T 4 /* VSRampTime bit position */ +#define VSSLAM_MASK 0xfffffff8 /* MaskOff [VSSlamTime] */ #define PWR_PLN_SHIFT 28 /* PwrPlanes bit shift */ #define PWR_PLN_ON 0x10000000 /* PwrPlanes bit ON */ #define PWR_PLN_OFF 0x0efffffff /* PwrPlanes bit OFF */ |