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| author | Yinghai Lu <yinghailu@gmail.com> | 2005-01-26 17:57:34 +0000 |
|---|---|---|
| committer | Yinghai Lu <yinghailu@gmail.com> | 2005-01-26 17:57:34 +0000 |
| commit | ff8b96ec51eab90b593ca181e5bf1f3d03e4f114 (patch) | |
| tree | 9093be725ae120c84089ce57ff3f414923cf9257 /src/northbridge | |
| parent | eb2b06bc3fa6bfaa6ba597629495f39e244d8b5e (diff) | |
| download | coreboot-ff8b96ec51eab90b593ca181e5bf1f3d03e4f114.tar.xz | |
pre_d0
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/amdk8/coherent_ht.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index d22a171945..3588e523f8 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -1557,7 +1557,7 @@ static int apply_cpu_errata_fixes(unsigned nodes, int needs_reset) } } - else if(is_cpu_pre_d0()) { // d0 later don't need it + else { uint32_t cmd_ref; /* Errata 98 * Set Clk Ramp Hystersis to 7 |