summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2018-06-03 12:26:58 +0200
committerArthur Heymans <arthur@aheymans.xyz>2018-06-05 07:58:57 +0000
commit02b13fd8cdfbfcb4858ec0e6f66688b96950198e (patch)
tree1faac362cb685c090ac6b2ccc08feb9f9e44235b /src/northbridge
parent6fcd7b8eb1ee650daa939593e8cbb3939f7c1188 (diff)
downloadcoreboot-02b13fd8cdfbfcb4858ec0e6f66688b96950198e.tar.xz
cpu/intel/model_2065x: Switch to POSTCAR_STAGE
Also removes some non-POSTCAR_STAGE functions, since those are unused now. Change-Id: I439bffbe39411186355d374eed7d5efd63fb02e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/26792 Reviewed-by: Matthias Gazzari <mail@qtux.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/nehalem/Kconfig2
-rw-r--r--src/northbridge/intel/nehalem/Makefile.inc2
-rw-r--r--src/northbridge/intel/nehalem/ram_calc.c14
3 files changed, 11 insertions, 7 deletions
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 573fdfe208..4689c1a096 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -24,6 +24,8 @@ config NORTHBRIDGE_INTEL_NEHALEM
select CACHE_MRC_SETTINGS
select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
+ select POSTCAR_STAGE
+ select POSTCAR_CONSOLE
if NORTHBRIDGE_INTEL_NEHALEM
diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index acb828c1c5..6722621ba1 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -29,4 +29,6 @@ romstage-y += ../../../arch/x86/walkcbfs.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+postcar-y += ram_calc.c
+
endif
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index bbf84f98d7..a8c33a04ff 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -39,9 +39,10 @@ void *cbmem_top(void)
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
-/* setup_stack_and_mtrrs() determines the stack to use after
- * cache-as-ram is torn down as well as the MTRR settings to use. */
-void *setup_stack_and_mtrrs(void)
+/* platform_enter_postcar() determines the stack to use after
+ * cache-as-ram is torn down as well as the MTRR settings to use,
+ * and continues execution in postcar stage. */
+void platform_enter_postcar(void)
{
struct postcar_frame pcf;
uintptr_t top_of_ram;
@@ -63,8 +64,7 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
- /* Save the number of MTRRs to setup. Return the stack location
- * pointing to the number of MTRRs.
- */
- return postcar_commit_mtrrs(&pcf);
+ run_postcar_phase(&pcf);
+
+ /* We do not return here. */
}