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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-01 11:21:53 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-04 00:53:39 +0200
commit032c23db08e6f0c6a2937092edafa26339aa4921 (patch)
treea2b840787cb06d3896524e19ffbeef709abfd965 /src/northbridge
parentfbdb085549b6c500e12dc2fb21143a197b4be042 (diff)
downloadcoreboot-032c23db08e6f0c6a2937092edafa26339aa4921.tar.xz
intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock. Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3584 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Nico Huber <nico.huber@secunet.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/Kconfig6
-rw-r--r--src/northbridge/intel/i945/bootblock.c24
-rw-r--r--src/northbridge/intel/i945/early_init.c1
3 files changed, 30 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index fbc9988f02..135cbe3cf8 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -24,6 +24,8 @@ if NORTHBRIDGE_INTEL_I945
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
+ select MMCONF_SUPPORT
+ select MMCONF_SUPPORT_DEFAULT
select HAVE_DEBUG_RAM_SETUP
select LAPIC_MONOTONIC_TIMER
@@ -32,6 +34,10 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
def_bool n
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/intel/i945/bootblock.c"
+
config VGA_BIOS_ID
string
default "8086,27a2"
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
new file mode 100644
index 0000000000..4571446cae
--- /dev/null
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -0,0 +1,24 @@
+#include <arch/io.h>
+
+/* Just re-define this instead of including i945.h. It blows up romcc. */
+#define PCIEXBAR 0x48
+
+static void bootblock_northbridge_init(void)
+{
+ uint32_t reg;
+
+ /*
+ * The "io" variant of the config access is explicitly used to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * to true. That way all subsequent non-explicit config accesses use
+ * MCFG. This code also assumes that bootblock_northbridge_init() is
+ * the first thing called in the non-asm boot block code. The final
+ * assumption is that no assembly code is using the
+ * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ *
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under
+ * 4GiB.
+ */
+ reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
+ pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg);
+}
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d91930fe16..fd9f6b79b1 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -173,7 +173,6 @@ static void i945_setup_bars(void)
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);