diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
---|---|---|
committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/northbridge | |
parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
download | coreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
67 files changed, 387 insertions, 387 deletions
diff --git a/src/northbridge/amd/amdfam10/Config.lb b/src/northbridge/amd/amdfam10/Config.lb index 4f84115d77..f217fcdd3c 100644 --- a/src/northbridge/amd/amdfam10/Config.lb +++ b/src/northbridge/amd/amdfam10/Config.lb @@ -17,19 +17,19 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses AGP_APERTURE_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_HIGH_TABLES +uses CONFIG_AGP_APERTURE_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_HIGH_TABLES -default AGP_APERTURE_SIZE=0x4000000 -default HAVE_HIGH_TABLES=1 +default CONFIG_AGP_APERTURE_SIZE=0x4000000 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o driver misc_control.o -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object amdfam10_acpi.o makerule ssdt.c depends "$(TOP)/src/northbridge/amd/amdfam10/ssdt.dsl" diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h index d3fb11e349..4cca443716 100644 --- a/src/northbridge/amd/amdfam10/amdfam10.h +++ b/src/northbridge/amd/amdfam10/amdfam10.h @@ -958,9 +958,9 @@ that are corresponding to 0x01, 0x02, 0x03, 0x05, 0x06, 0x07 #ifdef __ROMCC__ #if NODE_NUMS==64 - #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CBB,(CDB+x),fn)):(PCI_DEV((CBB-1),(CDB+x-32),fn))) + #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) #else - #define NODE_PCI(x, fn) PCI_DEV(CBB,(CDB+x),fn) + #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) #endif #endif @@ -1025,7 +1025,7 @@ struct nodes_info_t { //#define MEM_CS_COPY 1 #define MEM_CS_COPY NODE_NUMS -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #define DQS_DELAY_COPY NODE_NUMS #else // #define DQS_DELAY_COPY 1 diff --git a/src/northbridge/amd/amdfam10/amdfam10_acpi.c b/src/northbridge/amd/amdfam10/amdfam10_acpi.c index 4651b17157..f902d6ee98 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_acpi.c +++ b/src/northbridge/amd/amdfam10/amdfam10_acpi.c @@ -134,7 +134,7 @@ unsigned long acpi_fill_slit(unsigned long current) /* fill the first 8 byte with that num */ /* fill the next num*num byte with distance, local is 10, 1 hop mean 20, and 2 hop with 30.... */ - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u8 *ln = sysinfox->ln; @@ -190,7 +190,7 @@ void update_ssdt(void *ssdt) u8 *CBST; u8 *CBBX; u8 *CBS2; - u8 *CBB2; + u8 *CONFIG_CBB2; int i; @@ -208,7 +208,7 @@ void update_ssdt(void *ssdt) HCDN = ssdt+0x57a; //+5 will be next HCDN CBBX = ssdt+0x61f; // CBST = ssdt+0x626; - CBB2 = ssdt+0x62d; // + CONFIG_CBB2 = ssdt+0x62d; // CBS2 = ssdt+0x634; for(i=0;i<HC_NUMS;i++) { @@ -245,9 +245,9 @@ void update_ssdt(void *ssdt) int_to_stream(0x20202020, HCDN + i*5); } - *CBBX = (u8)(CBB); + *CBBX = (u8)(CONFIG_CBB); - if(CBB == 0xff) { + if(CONFIG_CBB == 0xff) { *CBST = (u8) (0x0f); } else { if((sysconf.pci1234[0] >> 12) & 0xff) { //sb chain on other than bus 0 @@ -258,12 +258,12 @@ void update_ssdt(void *ssdt) } } - if((CBB == 0xff) && (sysconf.nodes>32)) { + if((CONFIG_CBB == 0xff) && (sysconf.nodes>32)) { *CBS2 = 0x0f; - *CBB2 = (u8)(CBB-1); + *CONFIG_CBB2 = (u8)(CONFIG_CBB-1); } else { *CBS2 = 0x00; - *CBB2 = 0x00; + *CONFIG_CBB2 = 0x00; } } diff --git a/src/northbridge/amd/amdfam10/amdfam10_conf.c b/src/northbridge/amd/amdfam10/amdfam10_conf.c index f7c6a3d3be..cd958c5216 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_conf.c +++ b/src/northbridge/amd/amdfam10/amdfam10_conf.c @@ -33,12 +33,12 @@ static struct dram_base_mask_t get_dram_base_mask(u32 nodeid) device_t dev; struct dram_base_mask_t d; #if defined(__ROMCC__) - dev = PCI_DEV(CBB, CDB, 1); + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1); #else dev = __f1_dev[0]; #endif -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // I will use ext space only for simple pci_write_config32(dev, 0x110, nodeid | (1<<28)); // [47:27] at [28:8] d.mask = pci_read_config32(dev, 0x114); // enable is bit 0 @@ -65,7 +65,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) { u32 i; device_t dev; -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // I will use ext space only for simple u32 d_base_i, d_base_d, d_mask_i, d_mask_d; d_base_i = nodeid | (0<<28); @@ -94,7 +94,7 @@ static void set_dram_base_mask(u32 nodeid, struct dram_base_mask_t d, u32 nodes) dev = __f1_dev[i]; #endif -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // I will use ext space only for simple pci_write_config32(dev, 0x110, d_base_i); pci_write_config32(dev, 0x114, d_base_d); //[47:27] at [28:8]; @@ -232,7 +232,7 @@ static u32 get_one_DCT(struct mem_info *meminfo) return one_DCT; } #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) { @@ -316,7 +316,7 @@ static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) #endif -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT static void set_addr_map_reg_4_6_in_one_node(u32 nodeid, u32 cfg_map_dest, u32 busn_min, u32 busn_max, u32 type) @@ -388,7 +388,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, busn_min>>=segbit; busn_max>>=segbit; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index < 4) { #endif tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min & 0xff)<<16)|((busn_max&0xff)<<24); @@ -400,7 +400,7 @@ static void set_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -429,7 +429,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 i; device_t dev; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif for(i=0; i<nodes; i++) { @@ -440,7 +440,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -458,7 +458,7 @@ static void clear_config_map_reg(u32 nodeid, u32 linkn, u32 ht_c_index, } -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS static u32 check_segn(device_t dev, u32 segbusn, u32 nodes, sys_info_conf_t *sysinfo) { @@ -488,7 +488,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, u32 tempreg; device_t dev; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif /* io range allocation */ @@ -510,7 +510,7 @@ static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, #endif pci_write_config32(dev, 0xC0 + ht_c_index * 8, tempreg); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -541,7 +541,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, { u32 i; device_t dev; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(ht_c_index<4) { #endif /* io range allocation */ @@ -554,7 +554,7 @@ static void clear_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index, pci_write_config32(dev, 0xC4 + ht_c_index * 8, 0); pci_write_config32(dev, 0xC0 + ht_c_index * 8, 0); } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } // : if hc_c_index > 3, We should use io_min, io_max to clear extend space @@ -592,7 +592,7 @@ static void re_set_all_config_map_reg(u32 nodes, u32 segbit, pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0); } } -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT u32 j; // clear the extend space for(j = 0; j< nodes; j++) { @@ -624,7 +624,7 @@ static u32 get_ht_c_index(u32 nodeid, u32 linkn, sys_info_conf_t *sysinfo) tempreg = 3 | ((nodeid & 0xf) <<4) | ((nodeid & 0x30)<<(12-4)) | (linkn<<8); for(ht_c_index=0;ht_c_index<4; ht_c_index++) { - reg = pci_read_config32(PCI_DEV(CBB, CDB, 1), 0xe0 + ht_c_index * 4); + reg = pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), 0xe0 + ht_c_index * 4); if(((reg & 0xffff) == 0x0000)) { /*found free*/ break; } @@ -660,7 +660,7 @@ static void store_ht_c_conf_bus(u32 nodeid, u32 linkn, u32 ht_c_index, static void set_BusSegmentEn(u32 node, u32 segbit) { -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS u32 dword; device_t dev; @@ -715,12 +715,12 @@ static void store_conf_io_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 io_min, u32 io_max) { u32 val; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ index = (reg-0xc0)>>3; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT } else { index+=4; } @@ -740,12 +740,12 @@ static void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max) { u32 val; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ index = (reg-0x80)>>3; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT } else { index+=8; } @@ -767,7 +767,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, u32 i; u32 tempreg; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ @@ -789,7 +789,7 @@ static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg, #endif for(i=0; i<sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } @@ -816,7 +816,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi u32 i; u32 tempreg; -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT if(reg!=0x110) { #endif /* io range allocation */ @@ -826,7 +826,7 @@ static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmi tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); for(i=0; i<sysconf.nodes; i++) pci_write_config32(__f1_dev[i], reg, tempreg); -#if EXT_CONF_SUPPORT +#if CONFIG_EXT_CONF_SUPPORT return; } diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c index a8b93b1818..b0aee4bccc 100644 --- a/src/northbridge/amd/amdfam10/debug.c +++ b/src/northbridge/amd/amdfam10/debug.c @@ -34,7 +34,7 @@ static void print_debug_addr(const char *str, void *val) static void print_debug_pci_dev(u32 dev) { -#if PCI_BUS_SEGN_BITS==0 +#if CONFIG_PCI_BUS_SEGN_BITS==0 printk_debug("PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); #else printk_debug("PCI: %04x:%02x:%02x.%02x", (dev>>28) & 0x0f, (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); diff --git a/src/northbridge/amd/amdfam10/early_ht.c b/src/northbridge/amd/amdfam10/early_ht.c index 43774ded3e..b1c21f2dd3 100644 --- a/src/northbridge/amd/amdfam10/early_ht.c +++ b/src/northbridge/amd/amdfam10/early_ht.c @@ -21,7 +21,7 @@ // mmconf is not ready yet static void set_bsp_node_CHtExtNodeCfgEn(void) { -#if EXT_RT_TBL_SUPPORT == 1 +#if CONFIG_EXT_RT_TBL_SUPPORT == 1 u32 dword; dword = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x68); dword |= (1<<27) | (1<<25); @@ -34,14 +34,14 @@ static void set_bsp_node_CHtExtNodeCfgEn(void) /* CHtExtAddrEn */ pci_io_write_config32(PCI_DEV(0, 0x18, 0), 0x68, dword); - // CPU on bus 0xff and 0xfe now. For now on we can use CBB and CDB. + // CPU on bus 0xff and 0xfe now. For now on we can use CONFIG_CBB and CONFIG_CDB. #endif } static void enumerate_ht_chain(void) { -#if HT_CHAIN_UNITID_BASE != 0 -/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), +#if CONFIG_HT_CHAIN_UNITID_BASE != 0 +/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. @@ -50,16 +50,16 @@ static void enumerate_ht_chain(void) * links needs to be programed to point at bus 0. */ unsigned next_unitid, last_unitid = 0; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 // let't record the device of last ht device, So we can set the - // Unitid to HT_CHAIN_END_UNITID_BASE + // Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; u8 real_last_pos = 0; int ht_dev_num = 0; // except host_bridge u8 end_used = 0; #endif - next_unitid = HT_CHAIN_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { u32 id; u8 hdr_type, pos; @@ -99,10 +99,10 @@ static void enumerate_ht_chain(void) unsigned ctrl, ctrl_off; device_t devx; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -112,7 +112,7 @@ static void enumerate_ht_chain(void) real_last_pos = pos; ht_dev_num++ ; #endif - #if HT_CHAIN_END_UNITID_BASE == 0 + #if CONFIG_HT_CHAIN_END_UNITID_BASE == 0 if (!next_unitid) goto out; #endif @@ -161,12 +161,12 @@ static void enumerate_ht_chain(void) } while(last_unitid != next_unitid); out: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { u16 flags; flags = pci_io_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_io_write_config16(PCI_DEV(0, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); } #endif diff --git a/src/northbridge/amd/amdfam10/get_pci1234.c b/src/northbridge/amd/amdfam10/get_pci1234.c index 1217a8be6b..f6a196aabf 100644 --- a/src/northbridge/amd/amdfam10/get_pci1234.c +++ b/src/northbridge/amd/amdfam10/get_pci1234.c @@ -49,7 +49,7 @@ * reset HC_POSSIBLE_NUM and update ssdt.dsl (hcdn, hclk) * * Put all the possible ht node/link to the list tp pci1234[] in get_bus_conf.c - * on MB dir. Also, don't forget to increase the ACPI_SSDTX_NUM etc if you have + * on MB dir. Also, don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc if you have * too much SSDT. How about co-processor on socket 1 on 2 way system. * or socket 2, and socket3 on 4 way system? treat that as one hc too! * diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 634fec53ce..a321a656d2 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -59,7 +59,7 @@ static void mcf3_read_resources(device_t dev) pci_dev_read_resources(dev); /* If we are not the first processor don't allocate the gart apeture */ - if (dev->path.pci.devfn != PCI_DEVFN(CDB, 3)) { + if (dev->path.pci.devfn != PCI_DEVFN(CONFIG_CDB, 3)) { return; } @@ -69,7 +69,7 @@ static void mcf3_read_resources(device_t dev) if (iommu) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?AGP_APERTURE_SIZE:1; + resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 6a9504ccc1..fa7cb6db00 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -42,7 +42,7 @@ #include "amdfam10.h" -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #include <cpu/amd/model_10xxx_rev.h> #endif @@ -60,13 +60,13 @@ device_t get_node_pci(u32 nodeid, u32 fn) { #if NODE_NUMS == 64 if(nodeid<32) { - return dev_find_slot(CBB, PCI_DEVFN(CDB + nodeid, fn)); + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); } else { - return dev_find_slot(CBB-1, PCI_DEVFN(CDB + nodeid - 32, fn)); + return dev_find_slot(CONFIG_CBB-1, PCI_DEVFN(CONFIG_CDB + nodeid - 32, fn)); } #else - return dev_find_slot(CBB, PCI_DEVFN(CDB + nodeid, fn)); + return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB + nodeid, fn)); #endif } @@ -83,7 +83,7 @@ static void get_fx_devs(void) __f4_dev[i] = get_node_pci(i, 4); } if (!__f1_dev[0]) { - printk_err("Cannot find %02x:%02x.1", CBB, CDB); + printk_err("Cannot find %02x:%02x.1", CONFIG_CBB, CONFIG_CDB); die("Cannot go on\n"); } } @@ -113,14 +113,14 @@ static u32 amdfam10_nodeid(device_t dev) #if NODE_NUMS == 64 unsigned busn; busn = dev->bus->secondary; - if(busn != CBB) { - return (dev->path.pci.devfn >> 3) - CDB + 32; + if(busn != CONFIG_CBB) { + return (dev->path.pci.devfn >> 3) - CONFIG_CDB + 32; } else { - return (dev->path.pci.devfn >> 3) - CDB; + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } #else - return (dev->path.pci.devfn >> 3) - CDB; + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; #endif } @@ -156,7 +156,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, u32 busn = max&0xff; u32 max_devfn; -#if HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT==1 if(is_sublink1) { u32 regpos; u32 reg; @@ -187,7 +187,7 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, */ ht_c_index = get_ht_c_index(nodeid, link, &sysconf); -#if EXT_CONF_SUPPORT == 0 +#if CONFIG_EXT_CONF_SUPPORT == 0 if(ht_c_index>=4) return max; #endif @@ -196,12 +196,12 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, u32 link, u32 sblink, * so we set the subordinate bus number to 0xff for the moment. */ -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here min_bus = max; } - #if SB_HT_CHAIN_ON_BUS0 > 1 + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 // i would refined that to 2, 3, 4 ==> 0, 0x, 40, 0x80, 0xc0 // >4 will use more segments, We can have 16 segmment and every segment have 256 bus, For that case need the kernel support mmio pci config. @@ -295,9 +295,9 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max) // Put sb chain in bus 0 -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if(nodeid==0) { - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif max = amdfam10_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 @@ -305,18 +305,18 @@ static u32 amdfam10_scan_chains(device_t dev, u32 max) #endif -#if PCI_BUS_SEGN_BITS +#if CONFIG_PCI_BUS_SEGN_BITS max = check_segn(dev, max, sysconf.nodes, &sysconf); #endif for(link = 0; link < dev->links; link++) { -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; @@ -434,7 +434,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) resource = amdfam10_find_iopair(dev, nodeid, link); if (resource) { u32 align; -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext align = 8; } @@ -464,7 +464,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM | IORESOURCE_PREFETCH); -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -485,7 +485,7 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link) IORESOURCE_MEM | IORESOURCE_PREFETCH, IORESOURCE_MEM); -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 if((resource->index & 0x1fff) == 0x1110) { // ext normalize_resource(resource); } @@ -774,7 +774,7 @@ static u32 find_pci_tolm(struct bus *bus, u32 tolm) #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -786,7 +786,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < sysconf.nodes; i++) { @@ -840,7 +840,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i) u32 hole_sizek; u32 one_DCT; - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; @@ -911,7 +911,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int i) #endif -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -926,7 +926,7 @@ static void pci_domain_set_resources(device_t dev) u32 pci_tolm; int i, idx; u32 link; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; #endif @@ -1003,7 +1003,7 @@ static void pci_domain_set_resources(device_t dev) /* Round the mmio hold to 64M */ mmio_basek &= ~((64*1024) - 1); -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will * use hole_basek as mmio_basek and we don't need to reset hole. @@ -1023,7 +1023,7 @@ static void pci_domain_set_resources(device_t dev) if(reset_memhole) { if(mem_hole.node_id!=-1) { - /* We need to select HW_MEM_HOLE_SIZEK for raminit, it can not + /* We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too! We need to reset our Mem Hole, because We want more big HOLE than we already set @@ -1033,7 +1033,7 @@ static void pci_domain_set_resources(device_t dev) disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 // We need to double check if the mmio_basek is valid for hole // setting, if it is equal to basek, we need to decrease it some resource_t basek_pri; @@ -1089,7 +1089,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; @@ -1100,9 +1100,9 @@ static void pci_domain_set_resources(device_t dev) #endif } #if CONFIG_AMDMCT == 0 - #if HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) { - struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct mem_info *meminfo; meminfo = &sysinfox->meminfo[i]; sizek += hoist_memory(mmio_basek,i, get_one_DCT(meminfo), sysconf.nodes); @@ -1122,7 +1122,7 @@ static void pci_domain_set_resources(device_t dev) } ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { @@ -1150,7 +1150,7 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max) for(reg = 0xe0; reg <= 0xec; reg += 4) { f1_write_config32(reg, 0); } -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // all nodes for(i = 0; i< sysconf.nodes; i++) { int index; @@ -1164,7 +1164,7 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max) for(i=0;i<dev->links;i++) { - max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CDB, 0), 0xff, max); + max = pci_scan_bus(&dev->link[i], PCI_DEVFN(CONFIG_CDB, 0), 0xff, max); } /* Tune the hypertransport transaction for best performance. @@ -1197,7 +1197,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, #else .ops_pci_bus = &pci_cf8_conf1, @@ -1228,16 +1228,16 @@ static void sysconf_init(device_t dev) // first node sysconf.bsp_apicid = lapicid(); sysconf.apicid_offset = sysconf.bsp_apicid; -#if (ENABLE_APIC_EXT_ID == 1) +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) if (pci_read_config32(dev, 0x68) & (HTTC_APIC_EXT_ID|HTTC_APIC_EXT_BRD_CST)) { sysconf.enabled_apic_ext_id = 1; } - #if (APIC_ID_OFFSET>0) + #if (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { if(sysconf.bsp_apicid == 0) { /* bsp apic id is not changed */ - sysconf.apicid_offset = APIC_ID_OFFSET; + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; } else { sysconf.lift_bsp_apicid = 1; } @@ -1281,14 +1281,14 @@ static u32 cpu_bus_scan(device_t dev, u32 max) nb_cfg_54 = read_nb_cfg_54(); -#if CBB - dev_mc = dev_find_slot(0, PCI_DEVFN(CDB, 0)); //0x00 +#if CONFIG_CBB + dev_mc = dev_find_slot(0, PCI_DEVFN(CONFIG_CDB, 0)); //0x00 if(dev_mc && dev_mc->bus) { printk_debug("%s found", dev_path(dev_mc)); pci_domain = dev_mc->bus->dev; if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { printk_debug("\n%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CBB; // move to 0xff + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk_debug("%s",dev_path(dev_mc)); } else { @@ -1297,7 +1297,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) printk_debug("\n"); } - dev_mc = dev_find_slot(CBB, PCI_DEVFN(CDB, 0)); + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if(!dev_mc) { dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0)); if (dev_mc && dev_mc->bus) { @@ -1306,7 +1306,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if(pci_domain && (pci_domain->path.type == DEVICE_PATH_PCI_DOMAIN)) { if((pci_domain->links==1) && (pci_domain->link[0].children == dev_mc)) { printk_debug("%s move to ",dev_path(dev_mc)); - dev_mc->bus->secondary = CBB; // move to 0xff + dev_mc->bus->secondary = CONFIG_CBB; // move to 0xff printk_debug("%s\n",dev_path(dev_mc)); while(dev_mc){ printk_debug("%s move to ",dev_path(dev_mc)); @@ -1321,9 +1321,9 @@ static u32 cpu_bus_scan(device_t dev, u32 max) #endif - dev_mc = dev_find_slot(CBB, PCI_DEVFN(CDB, 0)); + dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0)); if (!dev_mc) { - printk_err("%02x:%02x.0 not found", CBB, CDB); + printk_err("%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); die(""); } @@ -1331,7 +1331,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) nodes = sysconf.nodes; -#if CBB && (NODE_NUMS > 32) +#if CONFIG_CBB && (NODE_NUMS > 32) if(nodes>32) { // need to put node 32 to node 63 to bus 0xfe if(pci_domain->links==1) { pci_domain->links++; // from 1 to 2 @@ -1340,7 +1340,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) pci_domain->link[1].children = 0; printk_debug("%s links increase to %d\n", dev_path(pci_domain), pci_domain->links); } - pci_domain->link[1].secondary = CBB - 1; + pci_domain->link[1].secondary = CONFIG_CBB - 1; } #endif /* Find which cpus are present */ @@ -1351,10 +1351,10 @@ static u32 cpu_bus_scan(device_t dev, u32 max) unsigned busn, devn; struct bus *pbus; - busn = CBB; - devn = CDB+i; + busn = CONFIG_CBB; + devn = CONFIG_CDB+i; pbus = dev_mc->bus; -#if CBB && (NODE_NUMS > 32) +#if CONFIG_CBB && (NODE_NUMS > 32) if(i>=32) { busn--; devn-=32; @@ -1381,7 +1381,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) */ int j; int linknum; -#if HT3_SUPPORT==1 +#if CONFIG_HT3_SUPPORT==1 linknum = 8; #else linknum = 4; @@ -1440,7 +1440,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max) if (cpu) { cpu->path.apic.node_id = i; cpu->path.apic.core_id = j; - #if (ENABLE_APIC_EXT_ID == 1) && (APIC_ID_OFFSET>0) + #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET>0) if(sysconf.enabled_apic_ext_id) { if(sysconf.lift_bsp_apicid) { cpu->path.apic.apic_id += sysconf.apicid_offset; diff --git a/src/northbridge/amd/amdfam10/raminit.h b/src/northbridge/amd/amdfam10/raminit.h index e446b54e6b..2d3a621b40 100644 --- a/src/northbridge/amd/amdfam10/raminit.h +++ b/src/northbridge/amd/amdfam10/raminit.h @@ -21,7 +21,7 @@ #define RAMINIT_H #if 0 -#if DIMM_SUPPORT==0x0110 +#if CONFIG_DIMM_SUPPORT==0x0110 //FBDIMM REG /* each channel can have 8 fbdimm */ #define DIMM_SOCKETS 8 @@ -42,7 +42,7 @@ struct mem_controller { #endif #endif -//#if (DIMM_SUPPORT & 0x00ff)==0x0004 +//#if (CONFIG_DIMM_SUPPORT & 0x00ff)==0x0004 //DDR2 REG and unbuffered : Socket F 1027 and AM3 /* every channel have 4 DDR2 DIMM for socket F * 2 for socket M2/M3 diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index fd967b5ebf..3ea22c5e4c 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -84,7 +84,7 @@ int mctRead_SPD(u32 smaddr, u32 reg) void mctSMBhub_Init(u32 node) { - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); activate_spd_rom(ctrl); } @@ -93,7 +93,7 @@ void mctSMBhub_Init(u32 node) void mctGet_DIMMAddr(struct DCTStatStruc *pDCTstat, u32 node) { int j; - struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); struct mem_controller *ctrl = &( sysinfo->ctrl[node] ); for(j=0;j<DIMM_SOCKETS;j++) { diff --git a/src/northbridge/amd/amdfam10/reset_test.c b/src/northbridge/amd/amdfam10/reset_test.c index 389d8e60a9..69869bf48c 100644 --- a/src/northbridge/amd/amdfam10/reset_test.c +++ b/src/northbridge/amd/amdfam10/reset_test.c @@ -43,7 +43,7 @@ static u32 cpu_init_detected(u8 nodeid) static u32 bios_reset_detected(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } @@ -51,7 +51,7 @@ static u32 bios_reset_detected(void) static u32 cold_reset_detected(void) { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } @@ -59,7 +59,7 @@ static u32 cold_reset_detected(void) static u32 other_reset_detected(void) // other warm reset not started by BIOS { u32 htic; - htic = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), HT_INIT_CONTROL); + htic = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && (htic & HTIC_BIOSR_Detect); } @@ -91,7 +91,7 @@ static void set_bios_reset(void) device_t dev; int i; - nodes = ((pci_read_config32(PCI_DEV(CBB, CDB, 0), 0x60) >> 4) & 7) + 1; + nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; for(i = 0; i < nodes; i++) { dev = NODE_PCI(i,0); @@ -115,7 +115,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b for(reg = 0xE0; reg < 0xF0; reg += 0x04) { u32 config_map; - config_map = pci_io_read_config32(PCI_DEV(CBB, CDB, 1), reg); + config_map = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1), reg); if ((config_map & 3) != 3) { continue; } @@ -126,7 +126,7 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b } } -#if EXT_CONF_SUPPORT == 1 +#if CONFIG_EXT_CONF_SUPPORT == 1 // let's check that in extend space // use the nodeid extend space to find out the bus for the linkn u32 tempreg; @@ -157,8 +157,8 @@ static u8 node_link_to_bus(u8 node, u8 link) // node are 6 bit, and link three b static u32 get_sblk(void) { u32 reg; - /* read PCI_DEV(CBB,CDB,0) 0x64 bit [8:9] to find out SbLink m */ - reg = pci_io_read_config32(PCI_DEV(CBB, CDB, 0), 0x64); + /* read PCI_DEV(CONFIG_CBB,CONFIG_CDB,0) 0x64 bit [8:9] to find out SbLink m */ + reg = pci_io_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x64); return ((reg>>8) & 3) ; } diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c index 49d546861c..4bfe03cf45 100644 --- a/src/northbridge/amd/amdfam10/resourcemap.c +++ b/src/northbridge/amd/amdfam10/resourcemap.c @@ -49,14 +49,14 @@ static void setup_default_resource_map(void) * This field defines the upper address bits of a 40 bit * address that define the end of the DRAM region. */ - PCI_ADDR(CBB, CDB, 1, 0x44), 0x0000f8f8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, - PCI_ADDR(CBB, CDB, 1, 0x54), 0x0000f8f8, 0x00000002, - PCI_ADDR(CBB, CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0x64), 0x0000f8f8, 0x00000004, - PCI_ADDR(CBB, CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, - PCI_ADDR(CBB, CDB, 1, 0x74), 0x0000f8f8, 0x00000006, - PCI_ADDR(CBB, CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x7C), 0x0000f8f8, 0x00000007, /* DRAM Base i Registers * F1:0x40 i = 0 * F1:0x48 i = 1 @@ -87,14 +87,14 @@ static void setup_default_resource_map(void) * This field defines the upper address bits of a 40-bit * address that define the start of the DRAM region. */ - PCI_ADDR(CBB, CDB, 1, 0x40), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x48), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x50), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x58), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x60), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x68), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x70), 0x0000f8fc, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x78), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x78), 0x0000f8fc, 0x00000000, /* Memory-Mapped I/O Limit i Registers * F1:0x84 i = 0 @@ -129,14 +129,14 @@ static void setup_default_resource_map(void) * address that defines the end of a memory-mapped * I/O region n */ - PCI_ADDR(CBB, CDB, 1, 0x84), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x8C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x94), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x9C), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xAC), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB4), 0x00000048, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xBC), 0x00000048, 0x00ffff00, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00, /* Memory-Mapped I/O Base i Registers * F1:0x80 i = 0 @@ -165,14 +165,14 @@ static void setup_default_resource_map(void) * address that defines the start of memory-mapped * I/O region i */ - PCI_ADDR(CBB, CDB, 1, 0x80), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x88), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x90), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0x98), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xA8), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB0), 0x000000f0, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003, /* PCI I/O Limit i Registers * F1:0xC4 i = 0 @@ -199,10 +199,10 @@ static void setup_default_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CBB, CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, - PCI_ADDR(CBB, CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, /* PCI I/O Base i Registers * F1:0xC0 i = 0 @@ -231,10 +231,10 @@ static void setup_default_resource_map(void) * This field defines the start of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CBB, CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, - PCI_ADDR(CBB, CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000, /* Config Base and Limit i Registers * F1:0xE0 i = 0 @@ -274,10 +274,10 @@ static void setup_default_resource_map(void) * This field defines the highest bus number in * configuration regin i */ - PCI_ADDR(CBB, CDB, 1, 0xE0), 0x0000FC88, 0xff000003, - PCI_ADDR(CBB, CDB, 1, 0xE4), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xE8), 0x0000FC88, 0x00000000, - PCI_ADDR(CBB, CDB, 1, 0xEC), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0xff000003, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, }; u32 max; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index ce3da289c5..906f155598 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -66,7 +66,7 @@ static u32 get_nodes(void) device_t dev; u32 nodes; - dev = PCI_DEV(CBB, CDB, 0); + dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0); nodes = ((pci_read_config32(dev, 0x60)>>4) & 7) ; #if CONFIG_MAX_PHYSICAL_CPUS > 8 nodes += (((pci_read_config32(dev, 0x160)>>4) & 7)<<3); @@ -116,9 +116,9 @@ void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0) */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List) { - const u8 swaplist[] = { 0xFF, HT_CHAIN_UNITID_BASE, HT_CHAIN_END_UNITID_BASE, 0xFF }; + const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ - if ((HT_CHAIN_UNITID_BASE != 0) && (HT_CHAIN_END_UNITID_BASE != 0)) { + if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { printk_debug("AMD_CB_ManualBUIDSwapList()\n"); if ((node == 0) && (link == 0)) { /* BSP SB link */ *List = swaplist; diff --git a/src/northbridge/amd/amdk8/Config.lb b/src/northbridge/amd/amdk8/Config.lb index bb38d7319a..40de82e04d 100644 --- a/src/northbridge/amd/amdk8/Config.lb +++ b/src/northbridge/amd/amdk8/Config.lb @@ -1,22 +1,22 @@ -uses AGP_APERTURE_SIZE -uses HAVE_ACPI_TABLES -uses HAVE_HIGH_TABLES -uses K8_REV_F_SUPPORT +uses CONFIG_AGP_APERTURE_SIZE +uses CONFIG_HAVE_ACPI_TABLES +uses CONFIG_HAVE_HIGH_TABLES +uses CONFIG_K8_REV_F_SUPPORT -default AGP_APERTURE_SIZE=0x4000000 -default HAVE_HIGH_TABLES=1 +default CONFIG_AGP_APERTURE_SIZE=0x4000000 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o driver misc_control.o -if K8_REV_F_SUPPORT +if CONFIG_K8_REV_F_SUPPORT makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit_f.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end else @@ -24,13 +24,13 @@ else makerule raminit_test depends "$(TOP)/src/northbridge/amd/amdk8/raminit_test.c" depends "$(TOP)/src/northbridge/amd/amdk8/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end end -if HAVE_ACPI_TABLES +if CONFIG_HAVE_ACPI_TABLES object amdk8_acpi.o end diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 5af58dea45..f03b93c9b5 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -2,7 +2,7 @@ #define AMDK8_H -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 #include "amdk8_f.h" #else #include "amdk8_pre_f.h" diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index d24a83c68f..bb5b2f7dd2 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -88,8 +88,8 @@ #define TRY_HIGH_FIRST 0 #endif -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef K8_HT_CHECK_PENDING_LINK @@ -104,8 +104,8 @@ #define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0 #endif -#ifndef ENABLE_APIC_EXT_ID - #define ENABLE_APIC_EXT_ID 0 +#ifndef CONFIG_ENABLE_APIC_EXT_ID + #define CONFIG_ENABLE_APIC_EXT_ID 0 #endif @@ -161,7 +161,7 @@ static void disable_probes(void) static void enable_apic_ext_id(u8 node) { -#if ENABLE_APIC_EXT_ID==1 +#if CONFIG_ENABLE_APIC_EXT_ID==1 #warning "FIXME Is the right place to enable apic ext id here?" u32 val; @@ -284,8 +284,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) freq_cap = pci_read_config16(dev, pos); freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */ -#if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) #endif { @@ -1591,13 +1591,13 @@ static unsigned verify_dualcore(unsigned nodes) static void coherent_ht_finalize(unsigned nodes) { unsigned node; -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 int rev_a0; #endif #if CONFIG_LOGICAL_CPUS==1 unsigned total_cpus; - if ((!HAVE_OPTION_TABLE) || + if ((!CONFIG_HAVE_OPTION_TABLE) || read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ total_cpus = verify_dualcore(nodes); } @@ -1613,7 +1613,7 @@ static void coherent_ht_finalize(unsigned nodes) */ print_spew("coherent_ht_finalize\r\n"); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { @@ -1644,7 +1644,7 @@ static void coherent_ht_finalize(unsigned nodes) (3 << HTTC_HI_PRI_BYP_CNT_SHIFT); pci_write_config32(dev, HT_TRANSACTION_CONTROL, val); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (rev_a0) { pci_write_config32(dev, 0x94, 0); pci_write_config32(dev, 0xb4, 0); @@ -1664,7 +1664,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) device_t dev; uint32_t cmd; dev = NODE_MC(node); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 66 diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 4ed376ae07..a445f253c7 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -91,7 +91,7 @@ static void dump_pci_device(unsigned dev) print_debug("\r\n"); } -#if K8_REV_F_SUPPORT == 1 +#if CONFIG_K8_REV_F_SUPPORT == 1 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 6cfecbddf7..bf80ef833e 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -4,8 +4,8 @@ // only for sb ht chain static void enumerate_ht_chain(void) { -#if HT_CHAIN_UNITID_BASE != 0 -/* HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ +#if CONFIG_HT_CHAIN_UNITID_BASE != 0 +/* CONFIG_HT_CHAIN_UNITID_BASE could be 0 (only one ht device in the ht chain), if so, don't need to go through the chain */ /* Assumption the HT chain that is bus 0 has the HT I/O Hub on it. * On most boards this just happens. If a cpu has multiple @@ -14,8 +14,8 @@ static void enumerate_ht_chain(void) */ unsigned next_unitid, last_unitid; device_t dev; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; // except host_bridge @@ -23,7 +23,7 @@ static void enumerate_ht_chain(void) #endif dev = PCI_DEV(0,0,0); - next_unitid = HT_CHAIN_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_UNITID_BASE; do { uint32_t id; uint8_t hdr_type, pos; @@ -63,10 +63,10 @@ static void enumerate_ht_chain(void) unsigned ctrl, ctrl_off; device_t devx; -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -126,13 +126,13 @@ static void enumerate_ht_chain(void) out: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) { uint16_t flags; dev = PCI_DEV(0,real_last_unitid, 0); flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(dev, real_last_pos + PCI_CAP_FLAGS, flags); } #endif diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c index f8c6744ed1..5c7ba00ff9 100644 --- a/src/northbridge/amd/amdk8/exit_from_self.c +++ b/src/northbridge/amd/amdk8/exit_from_self.c @@ -156,7 +156,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl, printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c index 85dd403a43..737f33b48d 100644 --- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c +++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c @@ -176,7 +176,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link) * Just put all the possible HT Node/link to the list tp pci1234[] in * src/mainboard/<vendor>/<mainboard>get_bus_conf.c * - * Also don't forget to increase the ACPI_SSDTX_NUM etc (FIXME what else) if + * Also don't forget to increase the CONFIG_ACPI_SSDTX_NUM etc (FIXME what else) if * you have too many SSDTs * * What about co-processor in socket 1 on a 2 way system? Or socket 2 and diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index 74c9f4fe4f..4c30a098e1 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -7,8 +7,8 @@ #include <device/pci_ids.h> #include <device/hypertransport_def.h> -#ifndef K8_HT_FREQ_1G_SUPPORT - #define K8_HT_FREQ_1G_SUPPORT 0 +#ifndef CONFIG_K8_HT_FREQ_1G_SUPPORT + #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif #ifndef RAMINIT_SYSINFO @@ -85,14 +85,14 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid device_t dev; //actually, only for one HT device HT chain, and unitid is 0 -#if HT_CHAIN_UNITID_BASE == 0 +#if CONFIG_HT_CHAIN_UNITID_BASE == 0 if(offset_unitid) { return; } #endif /* Check if is already collapsed */ - if((!offset_unitid) || (offset_unitid && (!((HT_CHAIN_END_UNITID_BASE == 0) && (HT_CHAIN_END_UNITID_BASE <HT_CHAIN_UNITID_BASE))))) { + if((!offset_unitid) || (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) { uint32_t id; dev = PCI_DEV(bus, 0, 0); id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -154,8 +154,8 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) /* AMD K8 Unsupported 1Ghz? */ if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) { - #if K8_HT_FREQ_1G_SUPPORT == 1 - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_e0()) { // only E0 later support 1GHz freq_cap &= ~(1 << HT_FREQ_1000Mhz); } @@ -303,7 +303,7 @@ static int ht_optimize_link( return needs_reset; } -#if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) +#if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) #if RAMINIT_SYSINFO == 1 static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo); @@ -425,7 +425,7 @@ static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned o static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) #endif { - //even HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link + //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link uint8_t next_unitid, last_unitid; unsigned uoffs; @@ -434,8 +434,8 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of int reset_needed = 0; #endif -#if HT_CHAIN_END_UNITID_BASE != 0x20 - //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid; uint8_t real_last_pos; int ht_dev_num = 0; @@ -443,7 +443,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of #endif uoffs = PCI_HT_HOST_OFFS; - next_unitid = (offset_unitid) ? HT_CHAIN_UNITID_BASE:1; + next_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1; do { uint32_t id; @@ -500,11 +500,11 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid) { if(next_unitid>= (bus ? 0x20:0x18) ) { if(!end_used) { - next_unitid = HT_CHAIN_END_UNITID_BASE; + next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE; end_used = 1; } else { goto out; @@ -560,18 +560,18 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } while (last_unitid != next_unitid ); -#if HT_CHAIN_END_UNITID_BASE != 0x20 +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 out: #endif end_of_chain: ; -#if HT_CHAIN_END_UNITID_BASE != 0x20 - if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) && !end_used ) { +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { uint16_t flags; int i; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; - flags |= HT_CHAIN_END_UNITID_BASE & 0x1f; + flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; pci_write_config16(PCI_DEV(bus, real_last_unitid, 0), real_last_pos + PCI_CAP_FLAGS, flags); #if RAMINIT_SYSINFO == 1 @@ -580,11 +580,11 @@ end_of_chain: ; { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; if(link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->udev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + link_pair->udev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); continue; } if(link_pair->dev == PCI_DEV(bus, real_last_unitid, 0)) { - link_pair->dev = PCI_DEV(bus, HT_CHAIN_END_UNITID_BASE, 0); + link_pair->dev = PCI_DEV(bus, CONFIG_HT_CHAIN_END_UNITID_BASE, 0); } } #endif @@ -605,7 +605,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) #endif { unsigned offset_unitid = 0; -#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif @@ -618,7 +618,7 @@ static int ht_setup_chain(device_t udev, unsigned upos) /* Make certain the HT bus is not enumerated */ ht_collapse_previous_enumeration(0, 0); -#if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif @@ -666,11 +666,11 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num) uint8_t val; unsigned devn = 1; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif - devn = HT_CHAIN_UNITID_BASE; + devn = CONFIG_HT_CHAIN_UNITID_BASE; #endif reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4); @@ -781,7 +781,7 @@ static int ht_setup_chains(uint8_t ht_c_num) unsigned regpos; uint32_t dword; uint8_t busn; - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) + #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) unsigned bus; #endif unsigned offset_unitid = 0; @@ -799,8 +799,8 @@ static int ht_setup_chains(uint8_t ht_c_num) pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword); - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if(i==0) // to check if it is sb ht chain #endif offset_unitid = 1; @@ -818,7 +818,7 @@ static int ht_setup_chains(uint8_t ht_c_num) reset_needed |= ht_setup_chainx(udev,upos,busn, offset_unitid); //all not #endif - #if (USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) + #if (CONFIG_USE_DCACHE_RAM == 1) && (K8_SCAN_PCI_BUS == 1) /* You can use use this in romcc, because there is function call in romcc, recursive will kill you */ bus = busn; // we need 32 bit #if RAMINIT_SYSINFO == 1 diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c index 1090d61b07..7c35082705 100644 --- a/src/northbridge/amd/amdk8/misc_control.c +++ b/src/northbridge/amd/amdk8/misc_control.c @@ -53,7 +53,7 @@ static void mcf3_read_resources(device_t dev) if (iommu) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?AGP_APERTURE_SIZE:1; + resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */ @@ -121,7 +121,7 @@ static void misc_control_init(struct device *dev) cmd = pci_read_config32(dev, 0x44); cmd |= (1<<6) | (1<<25); pci_write_config32(dev, 0x44, cmd ); -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 if (is_cpu_pre_c0()) { /* Errata 58 diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c index b6c0f7c8c0..c51bc21b03 100644 --- a/src/northbridge/amd/amdk8/northbridge.c +++ b/src/northbridge/amd/amdk8/northbridge.c @@ -155,12 +155,12 @@ static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned lin * We have no idea how many busses are behind this bridge yet, * so we set the subordinate bus number to 0xff for the moment. */ -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 // first chain will on bus 0 if((nodeid == 0) && (sblink==link)) { // actually max is 0 here min_bus = max; } - #if SB_HT_CHAIN_ON_BUS0 > 1 + #if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 // second chain will be on 0x40, third 0x80, forth 0xc0 else { min_bus = ((max>>6) + 1) * 0x40; @@ -257,8 +257,8 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) if(nodeid==0) { sblink = (pci_read_config32(dev, 0x64)>>8) & 3; -#if SB_HT_CHAIN_ON_BUS0 > 0 - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) offset_unitid = 1; #endif max = amdk8_scan_chain(dev, nodeid, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0 @@ -266,12 +266,12 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max) } for(link = 0; link < dev->links; link++) { -#if SB_HT_CHAIN_ON_BUS0 > 0 +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0 if( (nodeid == 0) && (sblink == link) ) continue; //already done #endif offset_unitid = 0; - #if ((HT_CHAIN_UNITID_BASE != 1) || (HT_CHAIN_END_UNITID_BASE != 0x20)) - #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 + #if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20)) + #if CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1 if((nodeid == 0) && (sblink == link)) #endif offset_unitid = 1; @@ -743,7 +743,7 @@ static uint32_t find_pci_tolm(struct bus *bus) #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH) #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { unsigned hole_startk; @@ -755,7 +755,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) struct hw_mem_hole_info mem_hole; int i; - mem_hole.hole_startk = HW_MEM_HOLE_SIZEK; + mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; mem_hole.node_id = -1; for (i = 0; i < FX_DEVS; i++) { @@ -893,7 +893,7 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i) } #endif -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -907,7 +907,7 @@ static void pci_domain_set_resources(device_t dev) unsigned long mmio_basek; uint32_t pci_tolm; int i, idx; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; unsigned reset_memhole = 1; #endif @@ -991,12 +991,12 @@ static void pci_domain_set_resources(device_t dev) mmio_basek &= ~((64*1024) - 1); #endif -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare mmio_basek and hole_basek * if mmio_basek is bigger that hole_basek and will use hole_basek as mmio_basek and we don't need to reset hole. * otherwise We reset the hole to the mmio_basek */ - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { #endif @@ -1010,13 +1010,13 @@ static void pci_domain_set_resources(device_t dev) //mmio_basek = 3*1024*1024; // for debug to meet boundary if(reset_memhole) { - if(mem_hole.node_id!=-1) { // We need to select HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! + if(mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....! // We need to reset our Mem Hole, because We want more big HOLE than we already set //Before that We need to disable mem hole at first, becase memhole could already be set on i+1 instead disable_hoist_memory(mem_hole.hole_startk, mem_hole.node_id); } - #if HW_MEM_HOLE_SIZE_AUTO_INC == 1 + #if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 //We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some uint32_t basek_pri; for (i = 0; i < FX_DEVS; i++) { @@ -1037,7 +1037,7 @@ static void pci_domain_set_resources(device_t dev) #endif } -#if K8_REV_F_SUPPORT == 0 +#if CONFIG_K8_REV_F_SUPPORT == 0 } // is_cpu_pre_e0 #endif @@ -1077,7 +1077,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, (idx | i), basek, pre_sizek); idx += 0x10; sizek -= pre_sizek; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 if (i==0 && high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; @@ -1087,9 +1087,9 @@ static void pci_domain_set_resources(device_t dev) } #endif } - #if HW_MEM_HOLE_SIZEK != 0 + #if CONFIG_HW_MEM_HOLE_SIZEK != 0 if(reset_memhole) - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 if(!is_cpu_pre_e0() ) #endif sizek += hoist_memory(mmio_basek,i); @@ -1111,7 +1111,7 @@ static void pci_domain_set_resources(device_t dev) if (sizek) ram_resource(dev, (idx | i), basek, sizek); idx += 0x10; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); if (i==0 && high_tables_base==0) { @@ -1211,7 +1211,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) sysconf.enabled_apic_ext_id = 1; if(bsp_apicid == 0) { /* bsp apic id is not changed */ - sysconf.apicid_offset = APIC_ID_OFFSET; + sysconf.apicid_offset = CONFIG_APIC_ID_OFFSET; } else { sysconf.lift_bsp_apicid = 1; @@ -1263,7 +1263,7 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max) // That is the typical case if(j == 0 ){ - #if K8_REV_F_SUPPORT == 0 + #if CONFIG_K8_REV_F_SUPPORT == 0 e0_later_single_core = is_e0_later_in_bsp(i); // single core #else e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index e55f4b898f..83ae83032a 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -553,7 +553,7 @@ static void hw_enable_ecc(const struct mem_controller *ctrl) if (nbcap & NBCAP_ECC) { dcl |= DCL_DimmEccEn; } - if (HAVE_OPTION_TABLE && + if (CONFIG_HAVE_OPTION_TABLE && read_option(CMOS_VSTART_ECC_memory, CMOS_VLEN_ECC_memory, 1) == 0) { dcl &= ~DCL_DimmEccEn; } @@ -867,7 +867,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else @@ -1104,7 +1104,7 @@ static void order_dimms(const struct mem_controller *ctrl) { unsigned long tom_k, base_k; - if ((!HAVE_OPTION_TABLE) || + if ((!CONFIG_HAVE_OPTION_TABLE) || read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) { tom_k = interleave_chip_selects(ctrl); } else { @@ -1408,7 +1408,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller * min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK]; bios_cycle_time = min_cycle_times[ read_option(CMOS_VSTART_max_mem_clock, CMOS_VLEN_max_mem_clock, 0)]; - if (HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { + if (CONFIG_HAVE_OPTION_TABLE && bios_cycle_time > min_cycle_time) { min_cycle_time = bios_cycle_time; } min_latency = 2; @@ -2111,7 +2111,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) return; } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2170,10 +2170,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_spew("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if hole_startk is valid. * If it is equal to the dram base address in K (base_k), * we need to decrease it. @@ -2328,7 +2328,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 // init hw mem hole here /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ if (!is_cpu_pre_e0()) diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 37398a8d23..0ad5e4758a 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -882,11 +882,11 @@ static void set_dimm_size(const struct mem_controller *ctrl, if (base0) { uint32_t dword; uint32_t ClkDis0; -#if CPU_SOCKET_TYPE == 0x10 /* L1 */ +#if CONFIG_CPU_SOCKET_TYPE == 0x10 /* L1 */ ClkDis0 = DTL_MemClkDis0; -#elif CPU_SOCKET_TYPE == 0x11 /* AM2 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x11 /* AM2 */ ClkDis0 = DTL_MemClkDis0_AM2; -#elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */ +#elif CONFIG_CPU_SOCKET_TYPE == 0x12 /* S1G1 */ ClkDis0 = DTL_MemClkDis0_S1g1; #endif @@ -1066,7 +1066,7 @@ static void set_top_mem(unsigned tom_k, unsigned hole_startk) * so I can see my rom chip and other I/O devices. */ if (tom_k >= 0x003f0000) { -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 if (hole_startk != 0) { tom_k = hole_startk; } else @@ -1452,7 +1452,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i u8 common_cl; /* S1G1 and AM2 sockets are Mod64BitMux capable. */ -#if CPU_SOCKET_TYPE == 0x11 || CPU_SOCKET_TYPE == 0x12 +#if CONFIG_CPU_SOCKET_TYPE == 0x11 || CONFIG_CPU_SOCKET_TYPE == 0x12 u8 mux_cap = 1; #else u8 mux_cap = 0; @@ -2341,7 +2341,7 @@ static void set_DramTerm(const struct mem_controller *ctrl, } -#if DIMM_SUPPORT == 0x0204 +#if CONFIG_DIMM_SUPPORT == 0x0204 odt = 0x2; /* 150 ohms */ #endif @@ -2512,7 +2512,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * long dimm_mask = meminfo->dimm_mask & 0x0f; -#if DIMM_SUPPORT==0x0104 /* DDR2 and REG */ +#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */ /* for REG DIMM */ dword = 0x00111222; dwordx = 0x002f0000; @@ -2536,7 +2536,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * #endif -#if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ +#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */ dword = 0x00111222; dwordx = 0x002F2F00; @@ -2576,7 +2576,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * } #endif -#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ +#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */ /* for UNBUF DIMM */ dword = 0x00111222; dwordx = 0x002f2f00; @@ -2658,7 +2658,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * printk_raminit("\tAddr Timing= %08x\n", dwordx); #endif -#if (DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ if (SlowAccessMode) { set_SlowAccessMode(ctrl); } @@ -2689,7 +2689,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info * static void set_RDqsEn(const struct mem_controller *ctrl, const struct mem_param *param, struct mem_info *meminfo) { -#if CPU_SOCKET_TYPE==0x10 +#if CONFIG_CPU_SOCKET_TYPE==0x10 //only need to set for reg and x8 uint32_t dch; @@ -2880,7 +2880,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, #include "raminit_f_dqs.c" -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,unsigned hole_startk, int i) { int ii; @@ -2941,10 +2941,10 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl) uint32_t hole_startk; int i; - hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK; + hole_startk = 4*1024*1024 - CONFIG_HW_MEM_HOLE_SIZEK; printk_raminit("Handling memory hole at 0x%08x (default)\n", hole_startk); -#if HW_MEM_HOLE_SIZE_AUTO_INC == 1 +#if CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC == 1 /* We need to double check if the hole_startk is valid, if it is equal to basek, we need to decrease it some */ uint32_t basek_pri; @@ -3143,7 +3143,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, printk_debug(" done\n"); } -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* init hw mem hole here */ /* DramHoleValid bit only can be set after MemClrStatus is set by Hardware */ set_hw_mem_hole(controllers, ctrl); @@ -3175,7 +3175,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 dqs_timing(controllers, ctrl, tsc0, sysinfo); #else @@ -3183,7 +3183,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, #endif #else -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 /* need to enable mtrr, so dqs training could access the test address */ setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -3195,18 +3195,18 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl, dqs_timing(i, &ctrl[i], sysinfo, 1); -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 break; // only train the first node with ram #endif } -#if MEM_TRAIN_SEQ == 2 +#if CONFIG_MEM_TRAIN_SEQ == 2 clear_mtrr_dqs(sysinfo->tom2_k); #endif #endif -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 wait_all_core0_mem_trained(sysinfo); #endif diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index e58a63053d..2764e606be 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -78,7 +78,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i uint32_t mem_base; unsigned nodeid = ctrl->node_id; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 uint32_t hole_reg; #endif @@ -91,7 +91,7 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_i mem_base &= 0xffff0000; dword += mem_base; -#if HW_MEM_HOLE_SIZEK != 0 +#if CONFIG_HW_MEM_HOLE_SIZEK != 0 hole_reg = sysinfo->hole_reg[nodeid]; if(hole_reg & 1) { unsigned hole_startk; @@ -855,7 +855,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st //restore SSE2 setting disable_sse2(); -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 /* We need tidy output for type 1 */ printk_debug(" CTLRMaxDelay=%02x\n", CTLRMaxDelay); #endif @@ -1702,7 +1702,7 @@ static unsigned int range_to_mtrr(unsigned int reg, align = max_align; } sizek = 1 << align; -#if MEM_TRAIN_SEQ != 1 +#if CONFIG_MEM_TRAIN_SEQ != 1 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n", reg, range_startk >>10, sizek >> 10, (type==MTRR_TYPE_UNCACHEABLE)?"UC": @@ -1921,7 +1921,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev) pci_write_config32(dev, DRAM_CONFIG_HIGH, reg); } -#if MEM_TRAIN_SEQ == 0 +#if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 static void dqs_timing(int controllers, const struct mem_controller *ctrl, tsc_t *tsc0, struct sys_info *sysinfo) #else @@ -2007,7 +2007,7 @@ out: #endif -#if MEM_TRAIN_SEQ > 0 +#if CONFIG_MEM_TRAIN_SEQ > 0 static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info *sysinfo, unsigned v) { @@ -2018,7 +2018,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info if(sysinfo->mem_trained[i] != 0x80) return; -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 //need to enable mtrr, so dqs training could access the test address setup_mtrr_dqs(sysinfo->tom_k, sysinfo->tom2_k); #endif @@ -2064,7 +2064,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info } out: -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 clear_mtrr_dqs(sysinfo->tom2_k); #endif @@ -2081,7 +2081,7 @@ out: } #endif -#if MEM_TRAIN_SEQ == 1 +#if CONFIG_MEM_TRAIN_SEQ == 1 static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox) { dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy @@ -2094,7 +2094,7 @@ static void copy_and_run_ap_code_in_car(unsigned ret_addr); static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); wait_till_sysinfo_in_ram(); // use pci to get it if(sysinfox->mem_trained[nodeid] == 0x80) { @@ -2105,7 +2105,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid]; memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller)); #else - memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE); + memcpy(sysinfo, sysinfox, CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); #endif set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's #if CONFIG_AP_CODE_IN_CAR == 0 diff --git a/src/northbridge/amd/gx1/Config.lb b/src/northbridge/amd/gx1/Config.lb index adb96c3c64..18b426d3b9 100644 --- a/src/northbridge/amd/gx1/Config.lb +++ b/src/northbridge/amd/gx1/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/gx1/northbridge.c b/src/northbridge/amd/gx1/northbridge.c index 63cc003df0..2c578d0671 100644 --- a/src/northbridge/amd/gx1/northbridge.c +++ b/src/northbridge/amd/gx1/northbridge.c @@ -126,7 +126,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -174,7 +174,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/amd/gx2/Config.lb b/src/northbridge/amd/gx2/Config.lb index 342dac967c..169db63065 100644 --- a/src/northbridge/amd/gx2/Config.lb +++ b/src/northbridge/amd/gx2/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o object chipsetinit.o object grphinit.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index bfcef1af47..f3a638ca5a 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -501,7 +501,7 @@ static struct device_operations cpu_bus_ops = { void chipsetInit (void); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -531,7 +531,7 @@ static void enable_dev(struct device *dev) dev->ops = &pci_domain_ops; pci_set_method(dev); tomk = ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/amd/lx/Config.lb b/src/northbridge/amd/lx/Config.lb index b9388893ab..340d3df9cb 100644 --- a/src/northbridge/amd/lx/Config.lb +++ b/src/northbridge/amd/lx/Config.lb @@ -1,6 +1,6 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o object northbridgeinit.o object grphinit.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 390c94cf78..c765377054 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -125,7 +125,7 @@ struct msr_defaults { */ void print_conf(void) { -#if DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR +#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR int i; unsigned long iol; msr_t msr; @@ -266,7 +266,7 @@ void print_conf(void) iol = inl(GPIO_MAPPER_X); printk_debug("IOR 0x%08X is now 0x%08X\n", GPIO_IO_BASE + GPIO_MAPPER_X, iol); -#endif //DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR +#endif //CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR } /* todo: add a resource record. We don't do this here because this may be called when @@ -415,7 +415,7 @@ static void ram_resource(device_t dev, unsigned long index, IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -436,7 +436,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tomk - 1024); // Systop - 1 MB -> KB -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.c b/src/northbridge/ibm/cpc710/cpc710_pci.c index 233e119baf..2b6024e5b9 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.c +++ b/src/northbridge/ibm/cpc710/cpc710_pci.c @@ -45,7 +45,7 @@ cpc710_pci_init(void) setCPC710_PCI32(CPC710_PCIL0_MSIZE, CPC710_PCI32_MEM_SIZE); setCPC710_PCI32(CPC710_PCIL0_IOSIZE, CPC710_PCI32_IO_SIZE); setCPC710_PCI32(CPC710_PCIL0_SMBAR, CPC710_PCI32_MEM_BASE); - setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32_IO_BASE); + setCPC710_PCI32(CPC710_PCIL0_SIBAR, CPC710_PCI32CONFIG_IO_BASE); setCPC710_PCI32(CPC710_PCIL0_CTLRW, 0x00000000); setCPC710_PCI32(CPC710_PCIL0_PSSIZE, 0x00000080); setCPC710_PCI32(CPC710_PCIL0_BARPS, 0x00000000); @@ -94,7 +94,7 @@ cpc710_pci_init(void) setCPC710_PCI64(CPC710_PCIL0_MSIZE, CPC710_PCI64_MEM_SIZE); setCPC710_PCI64(CPC710_PCIL0_IOSIZE, CPC710_PCI64_IO_SIZE); setCPC710_PCI64(CPC710_PCIL0_SMBAR, CPC710_PCI64_MEM_BASE); - setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64_IO_BASE); + setCPC710_PCI64(CPC710_PCIL0_SIBAR, CPC710_PCI64CONFIG_IO_BASE); setCPC710_PCI64(CPC710_PCIL0_CTLRW, 0x02000000); setCPC710_PCI64(CPC710_PCIL0_PSSIZE, 0x00000080); diff --git a/src/northbridge/ibm/cpc710/cpc710_pci.h b/src/northbridge/ibm/cpc710/cpc710_pci.h index 51aaa22049..0b3374ebd4 100644 --- a/src/northbridge/ibm/cpc710/cpc710_pci.h +++ b/src/northbridge/ibm/cpc710/cpc710_pci.h @@ -24,17 +24,17 @@ #ifndef _CPC710_PCI_H_ #define _CPC710_PCI_H_ -#define CPC710_PCI32_CONFIG (PCIC0_CFGADDR & 0xfff00000) +#define CPC710_PCI32_CONFIG (CONFIG_PCIC0_CFGADDR & 0xfff00000) #define CPC710_PCI32_MEM_SIZE 0xf8000000 #define CPC710_PCI32_MEM_BASE 0xc0000000 #define CPC710_PCI32_IO_SIZE 0xf8000000 -#define CPC710_PCI32_IO_BASE 0x80000000 +#define CPC710_PCI32CONFIG_IO_BASE 0x80000000 //#define CPC710_PCI64_CONFIG 0xff400000 //#define CPC710_PCI64_MEM_SIZE 0xf8000000 //#define CPC710_PCI64_MEM_BASE 0xc8000000 //#define CPC710_PCI64_IO_SIZE 0xf8000000 -//#define CPC710_PCI64_IO_BASE 0x88000000 +//#define CPC710_PCI64CONFIG_IO_BASE 0x88000000 #define CPC710_PCIL0_PSEA 0xf6110 #define CPC710_PCIL0_PCIDG 0xf6120 diff --git a/src/northbridge/intel/e7501/Config.lb b/src/northbridge/intel/e7501/Config.lb index 2a8095f692..72e903b9b1 100644 --- a/src/northbridge/intel/e7501/Config.lb +++ b/src/northbridge/intel/e7501/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h object northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c index 7168bf3112..06a68e1e47 100644 --- a/src/northbridge/intel/e7501/northbridge.c +++ b/src/northbridge/intel/e7501/northbridge.c @@ -65,7 +65,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -146,7 +146,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/e7520/Config.lb b/src/northbridge/intel/e7520/Config.lb index 03a78974d4..dbbd3aae24 100644 --- a/src/northbridge/intel/e7520/Config.lb +++ b/src/northbridge/intel/e7520/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o @@ -7,10 +7,10 @@ driver pciexp_porta1.o driver pciexp_portb.o driver pciexp_portc.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7520/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7520/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end diff --git a/src/northbridge/intel/e7520/northbridge.c b/src/northbridge/intel/e7520/northbridge.c index f2b2a0f3a0..47e6266aa6 100644 --- a/src/northbridge/intel/e7520/northbridge.c +++ b/src/northbridge/intel/e7520/northbridge.c @@ -76,7 +76,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -169,7 +169,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/e7525/Config.lb b/src/northbridge/intel/e7525/Config.lb index 07930ff434..fc3253d0ff 100644 --- a/src/northbridge/intel/e7525/Config.lb +++ b/src/northbridge/intel/e7525/Config.lb @@ -1,4 +1,4 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o @@ -7,10 +7,10 @@ driver pciexp_porta1.o driver pciexp_portb.o driver pciexp_portc.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 makerule raminit_test depends "$(TOP)/src/northbridge/intel/e7525/raminit_test.c" depends "$(TOP)/src/northbridge/intel/e7525/raminit.c" - action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" + action "$(CONFIG_HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@" end diff --git a/src/northbridge/intel/e7525/northbridge.c b/src/northbridge/intel/e7525/northbridge.c index 7900129ec2..65404d6bf3 100644 --- a/src/northbridge/intel/e7525/northbridge.c +++ b/src/northbridge/intel/e7525/northbridge.c @@ -76,7 +76,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -169,7 +169,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i3100/Config.lb b/src/northbridge/intel/i3100/Config.lb index 1534605dc0..6d0fa6f5be 100644 --- a/src/northbridge/intel/i3100/Config.lb +++ b/src/northbridge/intel/i3100/Config.lb @@ -17,11 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o driver pciexp_porta.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 928fe94c73..205e47db50 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -97,7 +97,7 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -190,7 +190,7 @@ static void pci_domain_set_resources(device_t dev) (remaplimitk + 64*1024) - remapbasek); } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i440bx/Config.lb b/src/northbridge/intel/i440bx/Config.lb index c9a26b08b3..a27625ee41 100644 --- a/src/northbridge/intel/i440bx/Config.lb +++ b/src/northbridge/intel/i440bx/Config.lb @@ -18,10 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i440bx/northbridge.c b/src/northbridge/intel/i440bx/northbridge.c index 31b5dc0575..34c868e0f3 100644 --- a/src/northbridge/intel/i440bx/northbridge.c +++ b/src/northbridge/intel/i440bx/northbridge.c @@ -90,7 +90,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -131,7 +131,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i82810/Config.lb b/src/northbridge/intel/i82810/Config.lb index 04375d89c1..2cc66fc2c0 100644 --- a/src/northbridge/intel/i82810/Config.lb +++ b/src/northbridge/intel/i82810/Config.lb @@ -18,10 +18,10 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 40c8ee0e69..4b3c321963 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -122,7 +122,7 @@ static int translate_i82810_to_mb[] = { /* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256, }; -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -172,7 +172,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i82830/Config.lb b/src/northbridge/intel/i82830/Config.lb index 863c867666..c6b7afd3d1 100644 --- a/src/northbridge/intel/i82830/Config.lb +++ b/src/northbridge/intel/i82830/Config.lb @@ -18,11 +18,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o driver vga.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index bf79ecdca1..9f6ba71d41 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -107,7 +107,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -149,7 +149,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 1024, tolmk - 1024); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i855gme/Config.lb b/src/northbridge/intel/i855gme/Config.lb index 83edd47783..04634806ab 100644 --- a/src/northbridge/intel/i855gme/Config.lb +++ b/src/northbridge/intel/i855gme/Config.lb @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h object northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i855gme/northbridge.c b/src/northbridge/intel/i855gme/northbridge.c index ec42c6eb73..ad48ee11de 100644 --- a/src/northbridge/intel/i855gme/northbridge.c +++ b/src/northbridge/intel/i855gme/northbridge.c @@ -88,7 +88,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev) /* ram_resource(dev, idx++, 1024, tolmk - 1024); */ ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i855pm/Config.lb b/src/northbridge/intel/i855pm/Config.lb index 2a8095f692..72e903b9b1 100644 --- a/src/northbridge/intel/i855pm/Config.lb +++ b/src/northbridge/intel/i855pm/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h object northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/intel/i855pm/northbridge.c b/src/northbridge/intel/i855pm/northbridge.c index 4fbd3b3cec..ce655a9f0d 100644 --- a/src/northbridge/intel/i855pm/northbridge.c +++ b/src/northbridge/intel/i855pm/northbridge.c @@ -66,7 +66,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -114,7 +114,7 @@ static void pci_domain_set_resources(device_t dev) ram_resource(dev, idx++, 0, 640); ram_resource(dev, idx++, 768, tolmk - 768); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; diff --git a/src/northbridge/intel/i945/Config.lb b/src/northbridge/intel/i945/Config.lb index 72f620e5ba..6b74fbe7c1 100644 --- a/src/northbridge/intel/i945/Config.lb +++ b/src/northbridge/intel/i945/Config.lb @@ -17,9 +17,9 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 config chip.h driver northbridge.o diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 81fd58e07f..b0ddbda7e4 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -93,7 +93,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 #define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB extern uint64_t high_tables_base, high_tables_size; #endif @@ -177,7 +177,7 @@ static void pci_domain_set_resources(device_t dev) assign_resources(&dev->link[0]); -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* Leave some space for ACPI, PIRQ and MP tables */ high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE * 1024; @@ -199,7 +199,7 @@ static struct device_operations pci_domain_ops = { .enable_resources = enable_childrens_resources, .init = 0, .scan_bus = pci_domain_scan_bus, -#if MMCONF_SUPPORT_DEFAULT +#if CONFIG_MMCONF_SUPPORT_DEFAULT .ops_pci_bus = &pci_ops_mmconf, #else .ops_pci_bus = &pci_cf8_conf1, diff --git a/src/northbridge/via/cn700/Config.lb b/src/northbridge/via/cn700/Config.lb index b824a17b75..e79e0e02e1 100644 --- a/src/northbridge/via/cn700/Config.lb +++ b/src/northbridge/via/cn700/Config.lb @@ -18,7 +18,7 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h @@ -28,4 +28,4 @@ driver northbridge.o driver agp.o driver vga.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 2d3adf1288..dc421d3e51 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -163,7 +163,7 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -206,7 +206,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c index 6cc885fd4b..3c8fb61ce6 100644 --- a/src/northbridge/via/cn700/vga.c +++ b/src/northbridge/via/cn700/vga.c @@ -49,10 +49,10 @@ static void vga_init(device_t dev) print_debug("Copying BOCHS BIOS to 0xf000\n"); /* - * Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM) + * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM) * This is for compatibility with the VGA ROM's BIOS callbacks. */ - memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000); + memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); printk_debug("Initializing VGA\n"); diff --git a/src/northbridge/via/cx700/Config.lb b/src/northbridge/via/cx700/Config.lb index 44299ba729..8f87759bce 100644 --- a/src/northbridge/via/cx700/Config.lb +++ b/src/northbridge/via/cx700/Config.lb @@ -15,7 +15,7 @@ ## along with this program; if not, write to the Free Software ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h @@ -28,4 +28,4 @@ driver cx700_lpc.o driver cx700_sata.o driver cx700_vga.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/cx700/northbridge.c b/src/northbridge/via/cx700/northbridge.c index c7bbb8bf85..7c09b9495b 100644 --- a/src/northbridge/via/cx700/northbridge.c +++ b/src/northbridge/via/cx700/northbridge.c @@ -87,7 +87,7 @@ static u32 find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -131,7 +131,7 @@ static void pci_domain_set_resources(device_t dev) tolmk -= 1024; // TOP 1M SM Memory } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/vt8601/Config.lb b/src/northbridge/via/vt8601/Config.lb index 9cf0154983..1523f98cfd 100644 --- a/src/northbridge/via/vt8601/Config.lb +++ b/src/northbridge/via/vt8601/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/vt8601/northbridge.c b/src/northbridge/via/vt8601/northbridge.c index b1e1c494cb..b58b8edf88 100644 --- a/src/northbridge/via/vt8601/northbridge.c +++ b/src/northbridge/via/vt8601/northbridge.c @@ -101,7 +101,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -147,7 +147,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/vt8623/Config.lb b/src/northbridge/via/vt8623/Config.lb index 9cf0154983..1523f98cfd 100644 --- a/src/northbridge/via/vt8623/Config.lb +++ b/src/northbridge/via/vt8623/Config.lb @@ -1,7 +1,7 @@ -uses HAVE_HIGH_TABLES +uses CONFIG_HAVE_HIGH_TABLES config chip.h driver northbridge.o -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 diff --git a/src/northbridge/via/vt8623/northbridge.c b/src/northbridge/via/vt8623/northbridge.c index 70ba59c1d2..41c472b568 100644 --- a/src/northbridge/via/vt8623/northbridge.c +++ b/src/northbridge/via/vt8623/northbridge.c @@ -253,7 +253,7 @@ static uint32_t find_pci_tolm(struct bus *bus) return tolm; } -#if HAVE_HIGH_TABLES==1 +#if CONFIG_HAVE_HIGH_TABLES==1 /* maximum size of high tables in KB */ #define HIGH_TABLES_SIZE 64 extern uint64_t high_tables_base, high_tables_size; @@ -299,7 +299,7 @@ static void pci_domain_set_resources(device_t dev) tolmk = tomk; } -#if HAVE_HIGH_TABLES == 1 +#if CONFIG_HAVE_HIGH_TABLES == 1 high_tables_base = (tolmk - HIGH_TABLES_SIZE) * 1024; high_tables_size = HIGH_TABLES_SIZE* 1024; printk_debug("tom: %lx, high_tables_base: %llx, high_tables_size: %llx\n", tomk*1024, high_tables_base, high_tables_size); diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c index 8f53975f89..1580d48acb 100644 --- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c +++ b/src/northbridge/via/vx800/examples/cache_as_ram_auto.c @@ -563,7 +563,7 @@ the following code is copied from src\mainboard\tyan\s2735\cache_as_ram_auto.c Only the code around CLEAR_FIRST_1M_RAM is changed. I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c" the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, -and cpu/x86/car/cache_as_ram_post.c do not cache my $XIP_ROM_BASE+SIZE area. +and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area. So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff withx86-version */ @@ -621,11 +621,11 @@ So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have #include "cpu/via/car/cache_as_ram_post.c" //#include "cpu/x86/car/cache_as_ram_post.c" __asm__ volatile ( - /* set new esp *//* before _RAMBASE */ + /* set new esp *//* before CONFIG_RAMBASE */ "subl %0, %%ebp\n\t" "subl %0, %%esp\n\t":: - "a" ((DCACHE_RAM_BASE + DCACHE_RAM_SIZE) - - _RAMBASE) + "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_RAMBASE) ); { diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c index d4e7e40dec..644284eef7 100644 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ b/src/northbridge/via/vx800/examples/chipset_init.c @@ -18,7 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 #include <arch/acpi.h> #endif #include <../northbridge/via/vx800/vx800.h> @@ -620,7 +620,7 @@ void init_VIA_chipset(void) void hardwaremain(int boot_complete) { struct lb_memory *lb_mem; -#if HAVE_ACPI_RESUME == 1 +#if CONFIG_HAVE_ACPI_RESUME == 1 void *wake_vec; #endif diff --git a/src/northbridge/via/vx800/romstrap.lds b/src/northbridge/via/vx800/romstrap.lds index 2e300c95a5..66159e3a1c 100644 --- a/src/northbridge/via/vx800/romstrap.lds +++ b/src/northbridge/via/vx800/romstrap.lds @@ -19,7 +19,7 @@ */ SECTIONS { - . = (_ROMBASE + ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); + . = (CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - 0x2c) - (__romstrap_end - __romstrap_start); .romstrap (.): { *(.romstrap) } |