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| author | Ronald G. Minnich <rminnich@gmail.com> | 2004-08-25 18:19:08 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2004-08-25 18:19:08 +0000 |
| commit | 1ddc8eaddb54b05a9ecb5ffbf9ba3e3264f63ec3 (patch) | |
| tree | c443b6d0290a96f6096022805ed9032c32740fcf /src/northbridge | |
| parent | e6552bcf3960c7d10fc3730a2d6b408bfc9a8ca9 (diff) | |
| download | coreboot-1ddc8eaddb54b05a9ecb5ffbf9ba3e3264f63ec3.tar.xz | |
more updates for 855
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i855pm/reset_test.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i855pm/reset_test.c b/src/northbridge/intel/i855pm/reset_test.c index 79a5cdaee1..29f2d45e8f 100644 --- a/src/northbridge/intel/i855pm/reset_test.c +++ b/src/northbridge/intel/i855pm/reset_test.c @@ -1,5 +1,5 @@ /* Convert to C by yhlu */ -#define MCH_DRC 0x7c +#define MCH_DRC 0x70 #define DRC_DONE (1 << 29) /* If I have already booted once skip a bunch of initialization */ /* To see if I have already booted I check to see if memory |