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authorNick High <nhigh@openmailbox.org>2016-04-26 17:22:05 -0400
committerMartin Roth <martinroth@google.com>2016-05-04 19:57:03 +0200
commit1e302cbd09bb304309476113c149c2c0d09a2a86 (patch)
tree9d1ce26aafac61185709e07cd9900d93638264e6 /src/northbridge
parent564dc9c7c89a94ff1b7803ef9937ca4f0dd95809 (diff)
downloadcoreboot-1e302cbd09bb304309476113c149c2c0d09a2a86.tar.xz
nb/intel/gm45: Fix native text mode initialization
The LVDS port is configured to accept data from pipe A, but the panel fitter and VGA were attached to pipe B. Changes to VGACNTRL: - select pipe A instead of pipe B. - disable VGA centering to fix jitter. TEST=Build and run on Thinkpad X200 in both text and framebuffer modes. Change-Id: I2356f264580d8b021952c217de3477291d866f98 Signed-off-by: Nick High <nhigh@openmailbox.org> Reviewed-on: https://review.coreboot.org/14524 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/gm45/gma.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 299cb252d8..a89f9bb571 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -340,7 +340,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPESRC(0), (639 << 16) | 399);
write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
- write32(mmio + PFIT_CONTROL, 0xa0000000);
+ write32(mmio + PFIT_CONTROL, 0x80000000);
}
mdelay(1);
@@ -362,12 +362,12 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
- write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE);
+ write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE);
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
| DISPPLANE_BGRX888);
mdelay(1);
} else {
- write32(mmio + VGACNTRL, 0x22c4008e);
+ write32(mmio + VGACNTRL, 0xc4008e);
}
write32(mmio + TRANS_HTOTAL(0),