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authorMarc Jones <marc.jones@se-eng.com>2012-11-02 14:26:44 -0600
committerRonald G. Minnich <rminnich@gmail.com>2012-11-14 05:39:19 +0100
commit313ec9d15bb8c56fc76eb40be920552cb231465e (patch)
tree5c409f649b1c478f1ed21795f6f0e152b0d4745d /src/northbridge
parent7e8c8e92bb7c754a759b7f3bf955f6fd95d44d86 (diff)
downloadcoreboot-313ec9d15bb8c56fc76eb40be920552cb231465e.tar.xz
Sandybridge: Set PEG clock gating
If the PEI System Agent doesn't run PCIe initialization, the PEG clock gating will not be setup. Add the PEG clock gating when pei_data->pcie_init is 0. Change-Id: I7e31bcebd11feb4807aa29b528adf09fb013c3ce Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/1827 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 2b46873e4d..b5a1c23f94 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -205,6 +205,13 @@ static void report_memory_config(void)
}
}
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+ /* If PCIe init is skipped, set the PEG clock gating */
+ if (!pei_data->pcie_init)
+ MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
+}
+
/**
* Find PEI executable in coreboot filesystem and execute it.
*
@@ -289,6 +296,7 @@ void sdram_initialize(struct pei_data *pei_data)
else
intel_early_me_status();
+ post_system_agent_init(pei_data);
report_memory_config();
/* S3 resume: don't save scrambler seed or MRC data */