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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-19 17:53:50 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-20 19:00:07 +0000
commit371e7d95aa640b4c815e71d2448f4c9b26c104bf (patch)
tree236134b147718b07ba45f571657704c4da60c9a1 /src/northbridge
parent4d991550b3a38346071da9dbdc0e7e96a6076082 (diff)
downloadcoreboot-371e7d95aa640b4c815e71d2448f4c9b26c104bf.tar.xz
nb/intel/e7505: Leave ROM as un-cacheable in postcar
Collected timestamps indicate LZMA decompression of ramstage is 4x slower when ROM is marked WP-cacheable, in contrast to having ROM as US. A simple copy WP->WB with uncompressed ramstage also appeared to be twice as slow as UC->WB copy. It should be noted that if POSTCAR_STAGE was removed from build, un-lzma takes 130 seconds instead of 45 milliseconds. Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/27164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/memmap.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c
index 48527fdd96..1b86012907 100644
--- a/src/northbridge/intel/e7505/memmap.c
+++ b/src/northbridge/intel/e7505/memmap.c
@@ -48,9 +48,12 @@ void platform_enter_postcar(void)
if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE))
die("Unable to initialize postcar frame.\n");
- /* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
+ /*
+ * Choose to NOT set ROM as WP cacheable here.
+ * Timestamps indicate the CPU this northbridge code is
+ * connected to, performs better for memcpy() and un-lzma
+ * operations when source is left as UC.
+ */
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);