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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-01 08:47:51 +0200
committerMartin Roth <martinroth@google.com>2018-10-11 21:06:53 +0000
commit419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 (patch)
tree8b5a5413e791e15d7e386c958b2a24899d8cddc2 /src/northbridge
parent603963e1ba4147ef31a72b94304708ab416e3b6a (diff)
downloadcoreboot-419bfbc1f1e7bb40c1e5698e1f50d4e275665d97.tar.xz
src: Move common IA-32 MSRs to <cpu/x86/msr.h>
Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/nehalem/early_init.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 0a9b408dcc..1ebb2a5ff3 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -110,11 +110,11 @@ static void early_cpu_init (void)
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
- m = rdmsr(MSR_IA32_MISC_ENABLES);
+ m = rdmsr(IA32_MISC_ENABLE);
m.hi &= ~0x00000040;
m.lo |= 0x10000;
- wrmsr(MSR_IA32_MISC_ENABLES, m);
+ wrmsr(IA32_MISC_ENABLE, m);
}
m = rdmsr(MSR_FSB_CLOCK_VCC);
@@ -124,9 +124,9 @@ static void early_cpu_init (void)
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
- m = rdmsr(MSR_IA32_MISC_ENABLES);
+ m = rdmsr(IA32_MISC_ENABLE);
m.lo |= 0x10000;
- wrmsr(MSR_IA32_MISC_ENABLES, m);
+ wrmsr(IA32_MISC_ENABLE, m);
}
void nehalem_early_initialization(int chipset_type)