- Changes to the pci config routines moving them closer to the non romcc API

  The goal is to have the same interface with or without romcc.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 35 insertions, 14 deletions

diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 9b799b3d31..81f044cc13 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -574,6 +574,8 @@ static void setup_coherent_ht_domain(void)
 	print_debug("setting up coherent ht domain....\r\n");
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	for(i = 0; i < max; i += 3) {
+		device_t dev;
+		unsigned where;
 		unsigned long reg;
 #if 0
 		print_debug_hex32(register_values[i]);
@@ -581,10 +583,18 @@ static void setup_coherent_ht_domain(void)
 		print_debug_hex32(register_values[i+2]);
 		print_debug("\r\n");
 #endif
+		dev = register_values[i] & ~0xff;
+		where = register_values[i] & 0xff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+#if 0
 		reg = pci_read_config32(register_values[i]);
 		reg &= register_values[i+1];
 		reg |= register_values[i+2] & ~register_values[i+1];
 		pci_write_config32(register_values[i], reg);
+#endif
 	}
 	print_debug("done.\r\n");
 }
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index 36e5b9a39f..b8262d519c 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -12,38 +12,38 @@ static void enumerate_ht_chain(void)
 		uint8_t hdr_type, pos;
 		last_unitid = next_unitid;
 
-		id = pci_read_config32(PCI_ADDR(0,0,0,PCI_VENDOR_ID));
+		id = pci_read_config32(PCI_DEV(0,0,0), PCI_VENDOR_ID);
 		/* If the chain is enumerated quit */
 		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
 			(((id >> 16) & 0xffff) == 0xffff) ||
 			(((id >> 16) & 0xffff) == 0x0000)) {
 			break;
 		}
-		hdr_type = pci_read_config8(PCI_ADDR(0,0,0,PCI_HEADER_TYPE));
+		hdr_type = pci_read_config8(PCI_DEV(0,0,0), PCI_HEADER_TYPE);
 		pos = 0;
 		hdr_type &= 0x7f;
 
 		if ((hdr_type == PCI_HEADER_TYPE_NORMAL) ||
 			(hdr_type == PCI_HEADER_TYPE_BRIDGE)) {
-			pos = pci_read_config8(PCI_ADDR(0,0,0, PCI_CAPABILITY_LIST));
+			pos = pci_read_config8(PCI_DEV(0,0,0), PCI_CAPABILITY_LIST);
 		}
 		while(pos != 0) {
 			uint8_t cap;
-			cap = pci_read_config8(PCI_ADDR(0,0,0, pos + PCI_CAP_LIST_ID));
+			cap = pci_read_config8(PCI_DEV(0,0,0), pos + PCI_CAP_LIST_ID);
 			if (cap == PCI_CAP_ID_HT) {
 				uint16_t flags;
-				flags = pci_read_config16(PCI_ADDR(0,0,0, pos + PCI_CAP_FLAGS));
+				flags = pci_read_config16(PCI_DEV(0,0,0), pos + PCI_CAP_FLAGS);
 				if ((flags >> 13) == 0) {
 					unsigned count;
 					flags &= ~0x1f;
 					flags |= next_unitid & 0x1f;
 					count = (flags >> 5) & 0x1f;
-					pci_write_config16(PCI_ADDR(0, 0, 0, pos + PCI_CAP_FLAGS), flags);
+					pci_write_config16(PCI_DEV(0, 0, 0), pos + PCI_CAP_FLAGS, flags);
 					next_unitid += count;
 					break;
 				}
 			}
-			pos = pci_read_config8(PCI_ADDR(0, 0, 0, pos + PCI_CAP_LIST_NEXT));
+			pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
 		}
 	} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
 }
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index 156b80a6a6..1f43e48671 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -692,6 +692,8 @@ static void sdram_set_registers(void)
 	print_debug("setting up CPU0 northbridge registers\r\n");
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	for(i = 0; i < max; i += 3) {
+		device_t dev;
+		unsigned where;
 		unsigned long reg;
 #if 0
 		print_debug_hex32(register_values[i]);
@@ -699,10 +701,19 @@ static void sdram_set_registers(void)
 		print_debug_hex32(register_values[i+2]);
 		print_debug("\r\n");
 #endif
+		dev = register_values[i] & ~0xff;
+		where = register_values[i] & 0xff;
+		reg = pci_read_config32(dev, where);
+		reg &= register_values[i+1];
+		reg |= register_values[i+2];
+		pci_write_config32(dev, where, reg);
+#if 0
+
 		reg = pci_read_config32(register_values[i]);
 		reg &= register_values[i+1];
 		reg |= register_values[i+2];
 		pci_write_config32(register_values[i], reg);
+#endif
 	}
 	print_debug("done.\r\n");
 }
@@ -727,10 +738,10 @@ static void sdram_set_registers(void)
 static void sdram_set_spd_registers(void) 
 {
 	unsigned long dcl;
-	dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
+	dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
 	/* Until I know what is going on disable ECC support */
 	dcl &= ~DCL_DimmEcEn;
-	pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl);
+	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
 }
 
 #define TIMEOUT_LOOPS 300000
@@ -739,23 +750,23 @@ static void sdram_enable(void)
 	unsigned long dcl;
 
 	/* Toggle DisDqsHys to get it working */
-	dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
+	dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
 	print_debug("dcl: ");
 	print_debug_hex32(dcl);
 	print_debug("\r\n");
 	dcl |= DCL_DisDqsHys;
-	pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl);
+	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
 	dcl &= ~DCL_DisDqsHys;
 	dcl &= ~DCL_DLL_Disable;
 	dcl &= ~DCL_D_DRV;
 	dcl &= ~DCL_QFC_EN;
 	dcl |= DCL_DramInit;
-	pci_write_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW), dcl);
+	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
 	
 	print_debug("Initializing memory: ");
 	int loops = 0;
 	do {
-		dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
+		dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
 		loops += 1;
 		if ((loops & 1023) == 0) {
 			print_debug(".");
@@ -771,7 +782,7 @@ static void sdram_enable(void)
 	print_debug("Clearing memory: ");
 	loops = 0;
 	do {
-		dcl = pci_read_config32(PCI_ADDR(0, 0x18, 2, DRAM_CONFIG_LOW));
+		dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
 		loops += 1;
 		if ((loops & 1023) == 0) {
 			print_debug(" ");