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author | Duncan Laurie <dlaurie@chromium.org> | 2012-07-16 12:19:00 -0700 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-26 20:32:45 +0200 |
commit | 556321167f3a3b4f4b934d114aca759387fddfaa (patch) | |
tree | 74546d2ae1d4d3c66b8b08efefa64c5558681b22 /src/northbridge | |
parent | d6aca0b7b14780a03c83e283f940f56c474a77dd (diff) | |
download | coreboot-556321167f3a3b4f4b934d114aca759387fddfaa.tar.xz |
CPU: Add option to set TCC activation offset
The default TCC activation offset is 0, which means TCC
activation starts at Tj_max. For devices with limited
cooling ability it may be desired to lower TCC activation.
This adds an option that can be declared in the devicetree
to set the TCC activation to a non-zero value.
Enable tcc_offset=15 in devicetree.cb and build/boot
the BIOS and check that the value is set in the MSR:
> and $(shr $(rdmsr 0 0x1a2) 24) 0xf
0xf
Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1343
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions