summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorPatrick Rudolph <siro@das-labor.org>2017-10-31 11:53:13 +0100
committerFelix Held <felix-coreboot@felixheld.de>2018-07-26 14:12:02 +0000
commit5af2deae92abd1258a752f29fbe48c91458706c2 (patch)
tree6c3a838c258fdc9fe3a2077fbf4ea2fcb4a229a4 /src/northbridge
parent652c491917dce44be6fe0bdce475824af3d43c87 (diff)
downloadcoreboot-5af2deae92abd1258a752f29fbe48c91458706c2.tar.xz
nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus width
The bus width has to be encoded where the lower 3 bits are the bus width in multiple of 8 and the following two bits give the error checking bits in multiple of 8. Hardcode to 64 bit as done on haswell. TODO: Make it dynamic once there's ECC support. Change-Id: I3b83a098205455b1c820d0436c6984938f261466 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index b31f28042a..e566057d85 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -113,7 +113,7 @@ static void fill_smbios17(ramctr_timing *ctrl)
info->dimm[channel][slot].part_number, 16);
dimm->mod_id = info->dimm[channel][slot].manufacturer_id;
dimm->mod_type = info->dimm[channel][slot].dimm_type;
- dimm->bus_width = info->dimm[channel][slot].width;
+ dimm->bus_width = MEMORY_BUS_WIDTH_64; // non-ECC only
mem_info->dimm_cnt++;
}
}