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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-07 11:00:50 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2020-01-12 16:02:55 +0000
commit61af679838ab52318641828b6a77c81229033c77 (patch)
tree36ea549af8cd0c6ffa5dbca29c318196b0e43dac /src/northbridge
parent9e581ec2264b39e7268fdf1dbcaaa82705111df9 (diff)
downloadcoreboot-61af679838ab52318641828b6a77c81229033c77.tar.xz
aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry()
Change-Id: I15aaefdf0c81f58adfeb6f4dde2f05b3c06fd145 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/e7505/Makefile.inc1
-rw-r--r--src/northbridge/intel/e7505/romstage.c49
2 files changed, 50 insertions, 0 deletions
diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc
index 9b68e13b9b..29ac4379cf 100644
--- a/src/northbridge/intel/e7505/Makefile.inc
+++ b/src/northbridge/intel/e7505/Makefile.inc
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_E7505),y)
ramstage-y += northbridge.c
ramstage-y += memmap.c
+romstage-y += romstage.c
romstage-y += raminit.c
romstage-y += memmap.c
diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c
new file mode 100644
index 0000000000..6c74c1febf
--- /dev/null
+++ b/src/northbridge/intel/e7505/romstage.c
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/romstage.h>
+
+#include <southbridge/intel/i82801dx/i82801dx.h>
+#include <northbridge/intel/e7505/raminit.h>
+
+void mainboard_romstage_entry(void)
+{
+ static const struct mem_controller memctrl[] = {
+ {
+ .d0 = PCI_DEV(0, 0, 0),
+ .d0f1 = PCI_DEV(0, 0, 1),
+ .channel0 = { 0x50, 0x52, 0, 0 },
+ .channel1 = { 0x51, 0x53, 0, 0 },
+ },
+ };
+
+ /* If this is a warm boot, some initialization can be skipped */
+ if (!e7505_mch_is_ready()) {
+ enable_smbus();
+
+ /* The real MCH initialisation. */
+ e7505_mch_init(memctrl);
+
+ /* Hook for post ECC scrub settings and debug. */
+ e7505_mch_done(memctrl);
+ }
+
+ printk(BIOS_DEBUG, "SDRAM is up.\n");
+
+ cbmem_recovery(0);
+}