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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-22 20:48:40 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-30 07:17:16 +0100
commit7d3045b517907d0827d5800b1bfb399a3df5ada7 (patch)
tree3f320950b5fad40e74177daeec88cae5fddc78b4 /src/northbridge
parentb316585eaf3dbaa14c3f8ccb704dd2e0d37ed5ea (diff)
downloadcoreboot-7d3045b517907d0827d5800b1bfb399a3df5ada7.tar.xz
AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdk8/Kconfig8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig
index 4b27689671..3f8861edd1 100644
--- a/src/northbridge/amd/amdk8/Kconfig
+++ b/src/northbridge/amd/amdk8/Kconfig
@@ -41,10 +41,6 @@ config WAIT_BEFORE_CPUS_INIT
bool
default n
-config MEM_TRAIN_SEQ
- int
- default 0
-
# Force 2T DRAM timing (vendor BIOS does it even for single DIMM setups and
# single DIMM is indeed unreliable without it).
config K8_FORCE_2T_DRAM_TIMING
@@ -104,6 +100,10 @@ if DIMM_DDR2
endif
endif #DIMM_DDR2
+config MEM_TRAIN_SEQ
+ int
+ default 0
+
endif #K8_REV_F_SUPPORT
config IOMMU