sb/intel/i82801ix: Add common code to set up LPC IO decode ranges

This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

2 files changed, 1 insertions, 2 deletions

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 430afe4077..5c28f533a9 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -435,7 +435,6 @@ u32 decode_tseg_size(u8 esmramc);
 void init_iommu(void);
 
 /* romstage mainboard hookups */
-void mb_setup_lpc(void);
 void mb_setup_superio(void); /* optional */
 void get_mb_spd_addrmap(u8 spd_addrmap[4]);
 void mb_pre_raminit_setup(sysinfo_t *); /* optional */
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index c853a3a1f4..7f45ca7f83 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -62,7 +62,7 @@ void mainboard_romstage_entry(void)
 	i82801ix_early_init();
 	setup_pch_gpios(&mainboard_gpio_map);
 
-	mb_setup_lpc();
+	i82801ix_lpc_decode();
 
 	mb_setup_superio();