summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorFurquan Shaikh <furquan@chromium.org>2017-02-20 13:41:56 -0800
committerFurquan Shaikh <furquan@google.com>2017-02-22 00:40:43 +0100
commitc248044b20d270d14cf460b04972b7ff741685d0 (patch)
tree837a8461b74772808c5c3324afb61d45d40b4d96 /src/northbridge
parentf4b20af9d716ff57d78d5d576e2990903bd70842 (diff)
downloadcoreboot-c248044b20d270d14cf460b04972b7ff741685d0.tar.xz
soc/intel/skylake: Fix broken suspend-resume
With recent change (a4b11e5c90: soc/intel/skylake: Perform CPU MP Init before FSP-S Init) to perform CPU MP init before FSP-S init, suspend resume is currently broken for all skylake/kabylake boards. All the skylake/kabylake boards store external stage cache in TSEG, which is relocated post MP-init. Thus, if FSP loading and initialization is done after MP-init, then ramstage is not able to: 1. Save FSP component in external stage cache during normal boot, and 2. Load FSP component from external stage cache during resume In order to fix this, ensure that FSP loading happens separately from FSP initialization. Add fsp_load callback for pre_mp_init which ensures that the required FSP component is loaded/saved from/to external stage cache. BUG=chrome-os-partner:63114 BRANCH=None TEST=Verified that 100 cycles of suspend/resume worked fine on poppy. Change-Id: I5b4deaf936a05b9bccf2f30b949674e2ba993488 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18414 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions