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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-03-16 10:19:51 -0700 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-03-16 23:17:28 +0100 |
| commit | cc6c615d29e926c74a7994e1bf70e56c0e9b7b6a (patch) | |
| tree | 0de47e3d0e02793d4aa1bac13e998348aefb555f /src/northbridge | |
| parent | 3ae1c651275a210dab0112825a44abc8c806aa16 (diff) | |
| download | coreboot-cc6c615d29e926c74a7994e1bf70e56c0e9b7b6a.tar.xz | |
Fix AMD Fam10 CBMEM allocation
The Fam10 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.
Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/794
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/agesa/family10/northbridge.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index b3e4c63d00..ee02f0d87a 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -29,6 +29,7 @@ #include <bitops.h> #include <cpu/cpu.h> #include <cpu/x86/lapic.h> +#include <cbmem.h> #if CONFIG_LOGICAL_CPUS==1 #include <pc80/mc146818rtc.h> @@ -907,11 +908,6 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB -extern uint64_t high_tables_base, high_tables_size; -#endif - #if CONFIG_GFXUMA == 1 extern uint64_t uma_memory_base, uma_memory_size; @@ -1062,13 +1058,13 @@ static void amdfam10_domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; - printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE, - high_tables_base); + high_tables_size = HIGH_MEMORY_SIZE; + printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", + (u32)(high_tables_size / 1024), high_tables_base); } #endif } @@ -1096,11 +1092,11 @@ static void amdfam10_domain_set_resources(device_t dev) if (high_tables_base==0) { /* Leave some space for ACPI, PIRQ and MP tables */ #if CONFIG_GFXUMA == 1 - high_tables_base = uma_memory_base - (HIGH_TABLES_SIZE * 1024); + high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE; #else - high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024; + high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE; #endif - high_tables_size = HIGH_TABLES_SIZE * 1024; + high_tables_size = HIGH_MEMORY_SIZE; } #endif } |