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authorArthur Heymans <arthur@aheymans.xyz>2019-11-12 23:34:13 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-15 16:45:48 +0000
commite27c013f39f0433dac57a754b3484553a536f30d (patch)
tree6e9b9d20964ac994c453079ca9c13cb145480dbd /src/northbridge
parentdc584c3f221bb59ee6b89e5517617b9d1d74bcf3 (diff)
downloadcoreboot-e27c013f39f0433dac57a754b3484553a536f30d.tar.xz
nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK
Console init in bootblock will be done in a separate CL. Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/Kconfig6
-rw-r--r--src/northbridge/intel/i945/Makefile.inc2
-rw-r--r--src/northbridge/intel/i945/bootblock.c7
3 files changed, 7 insertions, 8 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 0159bf2fde..5aa004d9eb 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -27,16 +27,14 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select PARALLEL_MP
+ select C_ENVIRONMENT_BOOTBLOCK
+ select NO_BOOTBLOCK_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n
config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
def_bool n
-config BOOTBLOCK_NORTHBRIDGE_INIT
- string
- default "northbridge/intel/i945/bootblock.c"
-
config VGA_BIOS_ID
string
default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 585d61b218..36dee6e571 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -15,6 +15,8 @@
ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I945),y)
+bootblock-y += bootblock.c
+
ramstage-y += memmap.c
ramstage-y += northbridge.c
ramstage-y += gma.c
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c
index 604088b1f3..e86abe5ab1 100644
--- a/src/northbridge/intel/i945/bootblock.c
+++ b/src/northbridge/intel/i945/bootblock.c
@@ -11,12 +11,11 @@
* GNU General Public License for more details.
*/
+#include <cpu/intel/car/bootblock.h>
#include <device/pci_ops.h>
+#include "i945.h"
-/* Just re-define this instead of including i945.h. It blows up romcc. */
-#define PCIEXBAR 0x48
-
-static void bootblock_northbridge_init(void)
+void bootblock_early_northbridge_init(void)
{
uint32_t reg;