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| author | Corey Osgood <corey.osgood@gmail.com> | 2010-08-01 17:20:20 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-08-01 17:20:20 +0000 |
| commit | f97654833adc12d9ebcceff633755e2dc9939158 (patch) | |
| tree | b6c0daf8c883acafb28a1f2b67f228e953f070b4 /src/northbridge | |
| parent | bc0f7a68df9c07518eb34ef4549a2f704ededcdd (diff) | |
| download | coreboot-f97654833adc12d9ebcceff633755e2dc9939158.tar.xz | |
Clarify a comment on an old hack, remove the call to early_mtrr_init
that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/via/cn700/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/via/cn700/raminit.c | 12 |
2 files changed, 8 insertions, 6 deletions
diff --git a/src/northbridge/via/cn700/northbridge.c b/src/northbridge/via/cn700/northbridge.c index 6afd760f83..dad7c468dd 100644 --- a/src/northbridge/via/cn700/northbridge.c +++ b/src/northbridge/via/cn700/northbridge.c @@ -177,7 +177,7 @@ static void pci_domain_set_resources(device_t dev) } tomk = rambits * 64 * 1024; - printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk); + printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk); /* Compute the Top Of Low Memory (TOLM), in Kb. */ tolmk = pci_tolm >> 10; if (tolmk >= tomk) { diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index 20b0afeb6e..acb40dc622 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -183,6 +183,8 @@ static void sdram_set_size(const struct mem_controller *ctrl) if (result == 0xff) die("DRAM module size too big, not supported by CN700\n"); + else + printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64); pci_write_config8(ctrl->d0f3, 0x40, result); pci_write_config8(ctrl->d0f3, 0x48, 0x00); @@ -400,18 +402,18 @@ static void sdram_enable(device_t dev, unsigned long rank_address) read32(rank_address + 0x10); /* 3. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); + PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n"); do_ram_command(dev, RAM_COMMAND_MRS); read32(rank_address + 0x120000); /* EMRS DLL Enable */ read32(rank_address + 0x800); /* MRS DLL Reset */ /* 4. Precharge all again. */ - PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n"); + PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n"); do_ram_command(dev, RAM_COMMAND_PRECHARGE); read32(rank_address + 0x0); /* 5. Perform 8 refresh cycles. Wait tRC each time. */ - PRINT_DEBUG_MEM("RAM Enable 3: CBR\n"); + PRINT_DEBUG_MEM("RAM Enable 5: CBR\n"); do_ram_command(dev, RAM_COMMAND_CBR); for (i = 0; i < 8; i++) { read32(rank_address + 0x20); @@ -419,7 +421,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) } /* 6. Mode register set. */ - PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n"); + PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n"); /* Safe value for now, BL=8, WR=5, CAS=4 */ /* * (E)MRS values are from the BPG. No direct explanation is given, but @@ -432,7 +434,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address) read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */ /* 8. Normal operation */ - PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n"); + PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n"); do_ram_command(dev, RAM_COMMAND_NORMAL); read32(rank_address + 0x30); } |