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authorArthur Heymans <arthur@aheymans.xyz>2019-06-05 13:36:55 +0200
committerNico Huber <nico.h@gmx.de>2019-06-17 08:15:04 +0000
commit01c83a2e9975f71d53772a535cf13d3e76a46827 (patch)
treed907f491291eb8d16b6394fc831bd13af23c5422 /src/northbridge
parent14774769daae489834473457712cd4c635ac1fbd (diff)
downloadcoreboot-01c83a2e9975f71d53772a535cf13d3e76a46827.tar.xz
3rdparty/blobs: Update submodule, SNB improvements
The sandybridge systemagent-r6 blob is modified: - To be more flexible about the location of the stack w.r.t. the heap - Place the MRC pool right below the MRC_VAR region - to work with the same DCACHE_RAM_BASE from the native raminit (could make the CAR linker symbols easily compatible if desired) This allows CAR setup compatibility between mrc.bin and native bootpath and also allows for BIOS/memory mappeds region larger than 8MB. This changes the semantics of CONFIG_DACHE_RAM_MRC_VAR_SIZE to also include the pool on top of MRC_VAR region. TESTED on T520 (boots and resumes from S3 with mrc.bin). Change-Id: I17d240656575b69a24718d90e4f2d2b7339d05a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33228 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig13
-rw-r--r--src/northbridge/intel/sandybridge/raminit_mrc.c26
2 files changed, 29 insertions, 10 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 4f9da000a4..59cf92c0ee 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -78,12 +78,13 @@ config MMCONF_BASE_ADDRESS
help
The MRC blob requires it to be at 0xf0000000.
-if USE_NATIVE_RAMINIT
-
config DCACHE_RAM_BASE
hex
default 0xfefe0000
+
+if USE_NATIVE_RAMINIT
+
config DCACHE_RAM_SIZE
hex
default 0x20000
@@ -96,17 +97,13 @@ endif # USE_NATIVE_RAMINIT
if !USE_NATIVE_RAMINIT
-config DCACHE_RAM_BASE
- hex
- default 0xff7e0000
-
config DCACHE_RAM_SIZE
hex
- default 0x1c000
+ default 0x17000
config DCACHE_RAM_MRC_VAR_SIZE
hex
- default 0x4000
+ default 0x9000
config MRC_FILE
string "Intel System Agent path and filename"
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index e88d356593..a8acfbf980 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -265,9 +265,31 @@ void sdram_initialize(struct pei_data *pei_data)
report_memory_config();
}
-/* These are the location and structure of MRC_VAR data in CAR. */
+/* These are the location and structure of MRC_VAR data in CAR.
+ The CAR region looks like this:
+ +------------------+ -> DCACHE_RAM_BASE
+ | |
+ | |
+ | COREBOOT STACK |
+ | |
+ | |
+ +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE
+ | |
+ | MRC HEAP |
+ | size = 0x5000 |
+ | |
+ +------------------+
+ | |
+ | MRC VAR |
+ | size = 0x4000 |
+ | |
+ +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE
+ + DCACHE_RAM_MRC_VAR_SIZE
+
+ */
#define DCACHE_RAM_MRC_VAR_BASE \
- (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)
+ (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + \
+ CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000)
struct mrc_var_data {
u32 acpi_timer_flag;