diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-13 10:03:31 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-19 08:17:06 +0000 |
| commit | 0ce41f1a116a816e774ebbd1130d27d7ee70e7e9 (patch) | |
| tree | 983a793e01bbf09ed1e9c74534d4b78f9d3f2866 /src/northbridge | |
| parent | 16f9bf83e00c786275d3fcc9d512d145ef6c93c9 (diff) | |
| download | coreboot-0ce41f1a116a816e774ebbd1130d27d7ee70e7e9.tar.xz | |
src: Add required space after "switch"
Change-Id: I85cf93e30606bc7838852bd300a369e79370629a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/agesa/family14/amdfam14_conf.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family16kb/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/h3ncmn.c | 2 | ||||
| -rw-r--r-- | src/northbridge/amd/amdht/ht_wrapper.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr23.c | 2 |
6 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/amd/agesa/family14/amdfam14_conf.c b/src/northbridge/amd/agesa/family14/amdfam14_conf.c index f78e3f55a4..0eabaa8842 100644 --- a/src/northbridge/amd/agesa/family14/amdfam14_conf.c +++ b/src/northbridge/amd/agesa/family14/amdfam14_conf.c @@ -126,7 +126,7 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev = vendev; - switch(vendev) { + switch (vendev) { case 0x10029809: case 0x10029808: case 0x10029807: diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 0361a77eb7..ae0830c731 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -964,7 +964,7 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev = vendev; - switch(vendev) { + switch (vendev) { case 0x10029900: /* AMD Radeon HD 7660G (Trinity) */ case 0x10029901: /* AMD Radeon HD 7660D (Trinity) */ case 0x10029903: /* AMD Radeon HD 7640G (Trinity) */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index b3b0ba192a..03db04235a 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -989,7 +989,7 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev = vendev; - switch(vendev) { + switch (vendev) { case 0x10029830: case 0x10029831: case 0x10029832: diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index 6173f17d5a..abb7458303 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1252,7 +1252,7 @@ static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode ******************************************************************************/ static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) { - switch(value) { + switch (value) { case 1: return 16; case 0: return 8; case 5: return 4; diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 05b8d12fdc..d005223d96 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -132,7 +132,7 @@ static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) } printk(log_level, ": "); - switch(event) { + switch (event) { case HT_EVENT_COH_EVENTS: case HT_EVENT_COH_NO_TOPOLOGY: case HT_EVENT_COH_LINK_EXCEED: diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 4e5c0ce923..32fa0d9cf0 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -820,7 +820,7 @@ static void program_dll(struct sysinfo *s) FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { const struct dll_setting *setting; - switch(s->selected_timings.mem_clk) { + switch (s->selected_timings.mem_clk) { default: /* Should not happen */ case MEM_CLOCK_667MHz: setting = default_ddr2_667_ctrl; |