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| author | Marc Jones <marc.jones@se-eng.com> | 2015-09-24 21:45:13 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-11-10 00:12:28 +0100 |
| commit | 31f4d00c95731be956110f4c76656c330fd4684f (patch) | |
| tree | 26ca7b7b3109203e6b21cfef711f4cac03af8c1c /src/northbridge | |
| parent | 5a4554a73f68247c4e00cb1a5d19fb504e9adb92 (diff) | |
| download | coreboot-31f4d00c95731be956110f4c76656c330fd4684f.tar.xz | |
northbridge/intel: Add i89xx header file
The Intel northbridge must be paired with a southbridge. Add
the ii89xx southbridge header based on the config setting.
Change-Id: Ied708006310efaba31afe6977ab7e57fe4e5ceec
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12167
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/report_platform.c | 5 |
2 files changed, 7 insertions, 2 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index f995b941e1..ab428c318f 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -55,8 +55,10 @@ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define DEFAULT_RCBABASE ((u8 *)0xfed1c000) -#if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) #include <southbridge/intel/fsp_bd82x6x/pch.h> +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) +#include <southbridge/intel/fsp_i89xx/pch.h> #endif /* Everything below this line is ignored in the DSDT */ diff --git a/src/northbridge/intel/fsp_sandybridge/report_platform.c b/src/northbridge/intel/fsp_sandybridge/report_platform.c index cd094bba88..004b57e004 100644 --- a/src/northbridge/intel/fsp_sandybridge/report_platform.c +++ b/src/northbridge/intel/fsp_sandybridge/report_platform.c @@ -18,8 +18,11 @@ #include <arch/cpu.h> #include <string.h> -#if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X + +#if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X) #include <southbridge/intel/fsp_bd82x6x/pch.h> +#elif IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_FSP_I89XX) +#include <southbridge/intel/fsp_i89xx/pch.h> #endif #include <arch/io.h> |