diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-01-26 13:28:56 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2019-01-27 10:39:54 +0000 |
| commit | 3452eca26dd8cda859636044efbb56e4a73d48a4 (patch) | |
| tree | 3422763a2d24ffc7c174bbfa9995a3f5a44f76a4 /src/northbridge | |
| parent | 2ef569a4050c3b0c3c93b3ffb6b4d804b3a7cddf (diff) | |
| download | coreboot-3452eca26dd8cda859636044efbb56e4a73d48a4.tar.xz | |
nb/intel/i945: Remove initialization already done at bootblock
Upper 128bytes of CMOS and RCBA are already enabled at bootblock.
Tested on 945g-MA. Resuming from suspend is working fine
Change-Id: I3f34380b0e700cf60688ad58465f9cb0aeda0928
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31107
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 3 |
2 files changed, 0 insertions, 7 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index be882de819..763300aee8 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -157,7 +157,6 @@ static void i945_setup_bars(void) /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80); /* ACPI_CNTL: Enable ACPI BAR */ @@ -174,9 +173,6 @@ static void i945_setup_bars(void) outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ printk(BIOS_DEBUG, " done.\n"); - /* Enable upper 128bytes of CMOS */ - RCBA32(RC) = (1 << 2); - printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 64c87dafc5..f3c3df68ac 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2414,9 +2414,6 @@ static void sdram_program_receive_enable(struct sys_info *sysinfo) { MCHBAR32(REPC) |= (1 << 0); - /* enable upper CMOS */ - RCBA32(0x3400) = (1 << 2); - /* Program Receive Enable Timings */ if (sysinfo->boot_path == BOOT_PATH_RESUME) { sdram_recover_receive_enable(); |