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authorAngel Pons <th3fanbus@gmail.com>2020-10-25 23:39:10 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-13 13:05:38 +0000
commit66e21d2d28576cd205afb1c5ed336222267a0dca (patch)
tree811b1910b637b7a44ab556985f25a87132434fae /src/northbridge
parentf11e2d06167614950d337525a2cff3cfcc33b4a2 (diff)
downloadcoreboot-66e21d2d28576cd205afb1c5ed336222267a0dca.tar.xz
nb/intel/haswell/acpi/peg.asl: Leverage ASL for DEVEN
There's no need to perform manual shifting and masking when ACPI allows one to painlessly describe bitfields of a register. The now-unused DVEN definition will be dropped in a follow-up, alongside other definitions. Change-Id: Iab6972c78c1114c8e3dfee28320ae233421ff154 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46787 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/acpi/peg.asl15
1 files changed, 12 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/acpi/peg.asl b/src/northbridge/intel/haswell/acpi/peg.asl
index 8dac128b8a..c63f3f9169 100644
--- a/src/northbridge/intel/haswell/acpi/peg.asl
+++ b/src/northbridge/intel/haswell/acpi/peg.asl
@@ -1,12 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+Field (\_SB.PCI0.MCHC.MCHP, DWordAcc, NoLock, Preserve)
+{
+ Offset (0x54),
+ , 1,
+ P2EN, 1,
+ P1EN, 1,
+ P0EN, 1,
+}
+
Device (PEGP)
{
Name (_ADR, 0x00010000)
Method (_STA)
{
- Return (((\_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf)
+ Return (P0EN * 0xf)
}
Device (DEV0)
@@ -21,7 +30,7 @@ Device (PEG1)
Method (_STA)
{
- Return (((\_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf)
+ Return (P1EN * 0xf)
}
Device (DEV0)
@@ -36,7 +45,7 @@ Device (PEG2)
Method (_STA)
{
- Return (((\_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf)
+ Return (P2EN * 0xf)
}
Device (DEV0)