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| author | Duncan Laurie <dlaurie@google.com> | 2018-12-10 11:32:23 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2018-12-14 18:30:58 +0000 |
| commit | 674c62bbee60e05b5830f3b4db85341d130d3d1f (patch) | |
| tree | b7dca43321ebb1d02370796b2ea68cfc589f1c74 /src/northbridge | |
| parent | 64c9f1584c63403207ee85b1d54ca594ae1fbedf (diff) | |
| download | coreboot-674c62bbee60e05b5830f3b4db85341d130d3d1f.tar.xz | |
soc/intel/cannonlake: Fix CNL-H GPIO pin map
The GPIO pin map for CNL-H does not match with the OS expected
pin numbers. This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.
I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c
Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions