summaryrefslogtreecommitdiff
path: root/src/northbridge
diff options
context:
space:
mode:
authorUwe Hermann <uwe@hermann-uwe.de>2007-05-04 00:51:17 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-05-04 00:51:17 +0000
commit7ea18cf5dd22caa62e4bb2a6369208eae53b179c (patch)
tree3fc96c5fe5abff12a2a7efb6d320506c38174dd2 /src/northbridge
parent6818245b1e4eb0db4c808b20b83d9e3ceb583d05 (diff)
downloadcoreboot-7ea18cf5dd22caa62e4bb2a6369208eae53b179c.tar.xz
Cosmetics (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i440bx/raminit.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 548444e337..08219741f0 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -242,7 +242,7 @@ static const long register_values[] = {
RPS, 0x0000, 0x0000,
/* SDRAMC - SDRAM Control Register
- * 0x76-0x77
+ * 0x76 - 0x77
*
* [15:10] Reserved
* [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT)
@@ -519,8 +519,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* 4. Mode register set. Wait two memory cycles. */
PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
- // TODO: Is 0x1d0 correct?
- // do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0000);
mdelay(10);
mdelay(10);