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authorNils Jacobs <njacobs8@hetnet.nl>2010-11-01 14:36:54 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-01 14:36:54 +0000
commit809e29ec8fdf49f65f87076005bbc778b9f10caa (patch)
tree287546b3d4598f559fda8aec8d9d17382560e29c /src/northbridge
parentfc9fcf7414c482a480ec9a87d32abd4a77ab1b26 (diff)
downloadcoreboot-809e29ec8fdf49f65f87076005bbc778b9f10caa.tar.xz
GX2: Clean up some white space and comments.
Also, add a copyright header to pll_reset.c. Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/gx2/pll_reset.c117
1 files changed, 73 insertions, 44 deletions
diff --git a/src/northbridge/amd/gx2/pll_reset.c b/src/northbridge/amd/gx2/pll_reset.c
index a434307035..19b0946346 100644
--- a/src/northbridge/amd/gx2/pll_reset.c
+++ b/src/northbridge/amd/gx2/pll_reset.c
@@ -1,3 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2010 Nils Jacobs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
#include <cpu/x86/tsc.h>
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
@@ -69,7 +89,7 @@ bad_ctc:
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
- * CPU Clock = sppl_raw_clk / VDIV
+ * CPU Clock = spll_raw_clk / VDIV
*/
/* table for Feedback divisor to FbDiv register value */
@@ -99,6 +119,15 @@ static const unsigned char pci33_ddr_crt [] = {
26, 2, 3 // 433/289
};
+/* FbDIV VDIV MDIV CPU/GeodeLink */
+/* 12 2 3 200/133 */
+/* 16 2 3 266/177 */
+/* 18 2 3 300/200 */
+/* 20 2 3 333/222 */
+/* 22 2 3 366/244 */
+/* 24 2 3 400/266 */
+/* 26 2 3 433/289 */
+
#if 0
static unsigned int get_memory_speed(void)
{
@@ -118,12 +147,12 @@ static unsigned int get_memory_speed(void)
///////////////////////////////////////////////////////////////////////////////
// Goodrich Version of pll_reset
-// PLLCHECK_COMPLETED is the "we've already done this" flag
+/* PLLCHECK_COMPLETED is the "we've already done this" flag */
#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
#ifndef RSTPPL_LOWER_BYPASS_SET
#define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
-#endif // RSTPPL_LOWER_BYPASS_SET
+#endif /* RSTPPL_LOWER_BYPASS_SET */
#define DEFAULT_MDIV 3
#define DEFAULT_VDIV 2
@@ -133,84 +162,84 @@ static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
unsigned MDIV_VDIV_FBDIV;
- unsigned SyncBits; // store the sync bits in up ebx
+ unsigned SyncBits; /* store the sync bits in up ebx */
- // clear the Bypass bit
+ /* clear the Bypass bit */
- // If the straps say we are in bypass and the syspll is not AND there are no software
- // bits set then FS2 or something set up the PLL and we should not change it.
+ /* If the straps say we are in bypass and the syspll is not AND there are no software */
+ /* bits set then FS2 or something set up the PLL and we should not change it. */
msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // If the "we've already been here" flag is set, don't reconfigure the pll
+ /* If the "we've already been here" flag is set, don't reconfigure the pll */
if ( !(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED ) )
- { // we haven't configured the PLL; do it now
+ { /* we haven't configured the PLL; do it now */
- // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
- // correct Strap Table.
+ /* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
+ /* correct Strap Table. */
post_code(POST_PLL_INIT);
- // configure for DDR
+ /* configure for DDR */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // Use Manual settings
- // UseManual:
+ /* Use Manual settings */
+ /* UseManual: */
post_code(POST_PLL_MANUAL);
- // DIV settings manually entered.
- // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
- // use gs and fs since we don't need them.
+ /* DIV settings manually entered. */
+ /* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
+ /* use gs and fs since we don't need them. */
- // ProgramClocks:
- // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
- // move everything into ebx
- // VDIV
+ /* ProgramClocks: */
+ /* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
+ /* move everything into ebx */
+ /* VDIV */
MDIV_VDIV_FBDIV = ((DEFAULT_VDIV - 2) << RSTPLL_UPPER_VDIV_SHIFT);
- // MDIV
+ /* MDIV */
MDIV_VDIV_FBDIV |= ((DEFAULT_MDIV - 2) << RSTPLL_UPPER_MDIV_SHIFT);
- // FbDIV
+ /* FbDIV */
MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);
- // write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values
+ /* write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
msrGlcpSysRstpll.hi = MDIV_VDIV_FBDIV;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // Set Reset, LockWait, and SW flag
- // DoReset:
+ /* Set Reset, LockWait, and SW flag */
+ /* DoReset: */
- // CheckSemiSync proc
- // Check for Semi-Sync in GeodeLink and CPU.
- // We need to do this here since the strap settings don't account for these bits.
+ /* CheckSemiSync proc */
+ /* Check for Semi-Sync in GeodeLink and CPU. */
+ /* We need to do this here since the strap settings don't account for these bits. */
SyncBits = 0; // store the sync bits in up ebx
- // Check for Bypass mode.
+ /* Check for Bypass mode. */
if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
{
- // If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will.
+ /* If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. */
SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
}
else
{
- // CheckPCIsync:
- // If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater
- // look up the real divider... if we get a 0 we have serious problems
+ /* CheckPCIsync: */
+ /* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
+ /* look up the real divider... if we get a 0 we have serious problems */
if ( !(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)) )
{
SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
}
- // CheckCPUSync:
- // If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync.
- // CPU is always greater or equal.
+ /* CheckCPUSync: */
+ /* If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync. */
+ /* CPU is always greater or equal. */
if (!((((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x07) + 2) %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_VDIV_SHIFT) & 0x0F) + 2)))
{
@@ -219,29 +248,29 @@ static void pll_reset(void)
}
- // SetSync:
+ /* SetSync: */
msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
msrGlcpSysRstpll.lo |= SyncBits;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // CheckSemiSync endp
+ /* CheckSemiSync endp */
- // now we do the reset
- // Set hold count to 99 (063h)
+ /* now we do the reset */
+ /* Set hold count to 99 (063h) */
msrGlcpSysRstpll.lo &= ~(0x0FF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= (0x0DE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= PLLCHECK_COMPLETED; // Say we are done
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // Don't want to use LOCKWAIT
+ /* Don't want to use LOCKWAIT */
msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);
msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
- // You should never get here..... The chip has reset.
+ /* You should never get here..... The chip has reset. */
post_code(POST_PLL_RESET_FAIL);
while (1);
- } // we haven't configured the PLL; do it now
+ } /* we haven't configured the PLL; do it now */
}
// End of Goodrich version of pll_reset