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authorDavid W. Hendricks <dwh@lanl.gov>2004-02-09 22:47:38 +0000
committerDavid W. Hendricks <dwh@lanl.gov>2004-02-09 22:47:38 +0000
commit854e45292b71a0f2777d8ec2edc0d9d6fd1326bf (patch)
tree7b89d727bc6ff8f42389b419d1cbdf4d7e943af1 /src/northbridge
parentc34d5ca790c5cad0c6366122b56fd8da02c5794a (diff)
downloadcoreboot-854e45292b71a0f2777d8ec2edc0d9d6fd1326bf.tar.xz
final merge of YhLu's stuff
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1371 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdk8/coherent_ht.c45
-rw-r--r--src/northbridge/amd/amdk8/misc_control.c26
-rw-r--r--src/northbridge/amd/amdk8/northbridge.c45
3 files changed, 99 insertions, 17 deletions
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 61880ec5f6..83e8404e94 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -100,6 +100,42 @@ static void disable_probes(void)
print_debug("done.\r\n");
}
+//BY LYH
+#if 0
+#define WAIT_TIMES 1000
+static void wait_ap_stop(u8 node)
+{
+ unsigned long reg;
+ unsigned long i;
+ for(i=0;i<WAIT_TIMES;i++) {
+ unsigned long regx;
+ regx = pci_read_config32(NODE_HT(node),0x6c);
+ if((regx & (1<<4))==1) break;
+ }
+ reg = pci_read_config32(NODE_HT(node),0x6c);
+ reg &= ~(1<<4); // clear it
+ pci_write_config32(NODE_HT(node), 0x6c, reg);
+
+}
+static void notify_bsp_ap_is_stopped(void)
+{
+ unsigned long reg;
+ unsigned long apic_id;
+ apic_id = *((volatile unsigned long *)(APIC_DEFAULT_BASE+APIC_ID));
+ apic_id >>= 24;
+/* print_debug("applicaton cpu apic_id: ");
+ print_debug_hex32(apic_id);
+ }*/
+ if(apic_id!=0) { //AP apic_id == node_id ??
+// set the ColdResetbit to notify BSP that AP is stopped
+ reg = pci_read_config32(NODE_HT(apic_id), 0x6C);
+ reg |= 1<<4;
+ pci_write_config32(NODE_HT(apic_id), 0x6C, reg);
+ }
+
+}
+#endif
+//BY LYH END
static void enable_routing(u8 node)
{
@@ -152,6 +188,15 @@ static void rename_temp_node(u8 node)
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
+//BY LYH
+#if 0
+ if(node!=0) {
+ wait_ap_stop(node);
+ }
+#endif
+//BY LYH END
+
+
print_debug(" done.\r\n");
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index 19e7c58ea4..501d766e4f 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -10,6 +10,7 @@
#include <device/pci_ops.h>
#include "./cpu_rev.c"
+static cpu_reset_count = 0; //By LYH
static void misc_control_init(struct device *dev)
{
uint32_t cmd;
@@ -52,27 +53,20 @@ static void misc_control_init(struct device *dev)
cmd = 0x04e20707;
pci_write_config32(dev, 0xd4, cmd );
}
-
-/*
- * FIXME: This preprocessor check is a mere workaround.
- * The right fix is to walk over all links on all nodes
- * and set the FIFO read pointer optimization value to
- * 0x25 for each link connected to an AMD HT device.
- *
- * The reason this is only enabled for machines with more
- * than one CPU is that Athlon64 machines don't have the
- * link at all that is optimized in the code.
- */
-
-#if CONFIG_MAX_CPUS > 1
+#if 1
+#if HAVE_HARD_RESET==1
+ cpu_reset_count++; //by LYH
cmd = pci_read_config32(dev, 0xdc);
if((cmd & 0x0000ff00) != 0x02500) {
cmd &= 0xffff00ff;
cmd |= 0x00002500;
pci_write_config32(dev, 0xdc, cmd );
- printk_debug("resetting cpu\n");
- hard_reset();
- }
+ if(cpu_reset_count==CONFIG_MAX_CPUS) { //By LYH
+ printk_debug("resetting cpu\n");
+ hard_reset();
+ } //By LYH
+ }
+#endif
#endif
printk_debug("done.\n");
}
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 249e497958..5e49e4b306 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -415,6 +415,13 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
limit |= rlimit & 0x01fff000;
limit |= (link & 3) << 4;
limit |= (nodeid & 3);
+ if (reg == 0xc8){
+ /* hack to set vga for test */
+ /* factory: b0: 03 0a 00 00 00 0b 00 00 */
+ f1_write_config32(0xb0, 0xa03);
+ f1_write_config32(0xb4, 0xb00);
+ base |= 0x30;
+ }
f1_write_config32(reg + 0x4, limit);
f1_write_config32(reg, base);
}
@@ -476,10 +483,45 @@ unsigned int amdk8_scan_root_bus(device_t root, unsigned int max)
return max;
}
+void amdk8_enable_resources(struct device *dev)
+{
+ uint16_t ctrl;
+ unsigned link;
+ unsigned int vgalink = -1;
+
+ ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+ ctrl |= dev->link[0].bridge_ctrl;
+ printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ printk_err("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+ pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+#if 0
+ /* let's see what link VGA is on */
+ for(link = 0; link < dev->links; link++) {
+ device_t child;
+ printk_err("Kid %d of k8: bridge ctrl says: 0x%x\n", link, dev->link[link].bridge_ctrl);
+ if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
+ vgalink = link;
+ }
+
+ if (vgalink != =1) {
+ /* now find the IOPAIR that goes to vgalink and set the vga enable in the base part (0x30) */
+ /* now allocate an MMIOPAIR and point it to the CPU0, LINK=vgalink */
+ /* now set IORR1 so it has a hole for the 0xa0000-0xcffff region */
+ }
+#endif
+
+ pci_dev_enable_resources(dev);
+ //enable_childrens_resources(dev);
+}
+
+
+
static struct device_operations northbridge_operations = {
.read_resources = amdk8_read_resources,
.set_resources = amdk8_set_resources,
- .enable_resources = pci_dev_enable_resources,
+// .enable_resources = pci_dev_enable_resources,
+ .enable_resources = amdk8_enable_resources,
.init = 0,
.scan_bus = amdk8_scan_chains,
.enable = 0,
@@ -496,3 +538,4 @@ struct chip_control northbridge_amd_amdk8_control = {
.name = "AMD K8 Northbridge",
.enumerate = enumerate,
};
+