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authorPatrick Georgi <patrick@georgi-clan.de>2013-02-09 15:56:04 +0100
committerPatrick Georgi <patrick@georgi-clan.de>2013-02-11 20:51:33 +0100
commit8cc846897132f6d6baa49118005815aefb5f560f (patch)
tree113b69cccb4728084be3c5f83f04fe9f56db43e5 /src/northbridge
parent3b19cbae37ab340bd530e35412800a171733fda6 (diff)
downloadcoreboot-8cc846897132f6d6baa49118005815aefb5f560f.tar.xz
Intel: Replace MSR 0xcd with MSR_FSB_FREQ
And move the corresponding #define to speedstep.h Change-Id: I8c884b8ab9ba54e01cfed7647a59deafeac94f2d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/2339 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/gm45/delay.c3
-rw-r--r--src/northbridge/intel/i3100/raminit.c3
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c5
-rw-r--r--src/northbridge/intel/i5000/raminit.c3
-rw-r--r--src/northbridge/intel/i5000/udelay.c3
-rw-r--r--src/northbridge/intel/i945/udelay.c3
6 files changed, 13 insertions, 7 deletions
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
index 50bea2c1c8..c33bbe2bf0 100644
--- a/src/northbridge/intel/gm45/delay.c
+++ b/src/northbridge/intel/gm45/delay.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
#include "delay.h"
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
@@ -45,7 +46,7 @@ static void _udelay(const u32 us, const u32 numerator, const int total)
u32 fsb = 0, divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index b453e8ba87..fa42efcac4 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -21,6 +21,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/intel/speedstep.h>
#include <stdlib.h>
#include "raminit.h"
#include "i3100.h"
@@ -583,7 +584,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
drc |= (1 << 4); /* independent clocks */
/* set front side bus speed */
- msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
+ msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
value = msr.lo & 0x07;
drc &= ~(3 << 2);
drc |= (fsb_conversion[value] << 2);
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 5fe206ff2a..4c688d55e9 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -20,6 +20,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/intel/speedstep.h>
#include "raminit_ep80579.h"
#include "ep80579.h"
@@ -441,8 +442,8 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
/* TODO check: */
/* set front side bus speed */
- msr = rdmsr(0xcd); /* returns 0 on Pentium M 90nm */
- print_debug("msr 0xcd = ");
+ msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
+ print_debug("MSR FSB_FREQ(0xcd) = ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index ffc579a32c..3c913cf66c 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -25,6 +25,7 @@
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
+#include <cpu/intel/speedstep.h>
#include <console/console.h>
#include <spd.h>
#include <types.h>
@@ -1560,7 +1561,7 @@ static int i5000_setup_clocking(struct i5000_fbd_setup *setup)
return 1;
}
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch(msr.lo & 7) {
case 1:
diff --git a/src/northbridge/intel/i5000/udelay.c b/src/northbridge/intel/i5000/udelay.c
index 6462fe0316..ff2da6f2a9 100644
--- a/src/northbridge/intel/i5000/udelay.c
+++ b/src/northbridge/intel/i5000/udelay.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
#include <console/console.h>
/**
* Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
@@ -35,7 +36,7 @@ void udelay(u32 us)
u32 d; /* ticks per us */
u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
index ce5e9d8943..be560085e1 100644
--- a/src/northbridge/intel/i945/udelay.c
+++ b/src/northbridge/intel/i945/udelay.c
@@ -22,6 +22,7 @@
#include <stdint.h>
#include <cpu/x86/tsc.h>
#include <cpu/x86/msr.h>
+#include <cpu/intel/speedstep.h>
/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
@@ -46,7 +47,7 @@ void udelay(u32 us)
u32 fsb = 0, divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xcd);
+ msr = rdmsr(MSR_FSB_FREQ);
switch (msr.lo & 0x07) {
case 5:
fsb = 400;