dpx114

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 322 insertions, 0 deletions

diff --git a/src/northbridge/transmeta/tm5800/Config.lb b/src/northbridge/transmeta/tm5800/Config.lb
new file mode 100644
index 0000000000..c4ed559da3
--- /dev/null
+++ b/src/northbridge/transmeta/tm5800/Config.lb
@@ -0,0 +1,5 @@
+
+config chip.h
+object northbridge.o
+driver misc_control.o
+
diff --git a/src/northbridge/transmeta/tm5800/chip.h b/src/northbridge/transmeta/tm5800/chip.h
new file mode 100644
index 0000000000..1c121ac077
--- /dev/null
+++ b/src/northbridge/transmeta/tm5800/chip.h
@@ -0,0 +1,5 @@
+struct northbridge_transmeta_tm5800_config
+{
+};
+
+extern struct chip_control northbridge_transmeta_tm5800_control;
diff --git a/src/northbridge/transmeta/tm5800/cpu_rev.c b/src/northbridge/transmeta/tm5800/cpu_rev.c
new file mode 100644
index 0000000000..b84b0b159c
--- /dev/null
+++ b/src/northbridge/transmeta/tm5800/cpu_rev.c
@@ -0,0 +1,15 @@
+/* this is a shrunken cpuid. */
+
+static unsigned int cpuid(unsigned int op)
+{
+	unsigned int ret;
+	unsigned dummy2,dummy3,dummy4;
+
+	asm volatile ( 
+		"cpuid" 
+		: "=a" (ret), "=b" (dummy2), "=c" (dummy3), "=d" (dummy4)
+		: "a" (op)
+		);
+
+	return ret;
+}
diff --git a/src/northbridge/transmeta/tm5800/debug.c b/src/northbridge/transmeta/tm5800/debug.c
new file mode 100644
index 0000000000..40296ee3c8
--- /dev/null
+++ b/src/northbridge/transmeta/tm5800/debug.c
@@ -0,0 +1,161 @@
+/*
+ * generic K8 debug code, used by mainboard specific auto.c
+ *
+ */
+
+static void print_debug_pci_dev(unsigned dev)
+{
+	print_debug("PCI: ");
+	print_debug_hex8((dev >> 16) & 0xff);
+	print_debug_char(':');
+	print_debug_hex8((dev >> 11) & 0x1f);
+	print_debug_char('.');
+	print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		print_debug_pci_dev(dev);
+		print_debug("\r\n");
+	}
+}
+
+static void dump_pci_device(unsigned dev)
+{
+	int i;
+	print_debug_pci_dev(dev);
+	print_debug("\r\n");
+	
+	for(i = 0; i <= 255; i++) {
+		unsigned char val;
+		if ((i & 0x0f) == 0) {
+			print_debug_hex8(i);
+			print_debug_char(':');
+		}
+		val = pci_read_config8(dev, i);
+		print_debug_char(' ');
+		print_debug_hex8(val);
+		if ((i & 0x0f) == 0x0f) {
+			print_debug("\r\n");
+		}
+	}
+}
+
+static void dump_pci_devices(void)
+{
+	device_t dev;
+	for(dev = PCI_DEV(0, 0, 0); 
+		dev <= PCI_DEV(0, 0x1f, 0x7); 
+		dev += PCI_DEV(0,0,1)) {
+		uint32_t id;
+		id = pci_read_config32(dev, PCI_VENDOR_ID);
+		if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0xffff) ||
+			(((id >> 16) & 0xffff) == 0x0000)) {
+			continue;
+		}
+		dump_pci_device(dev);
+	}
+}
+
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+	int i;
+	print_debug("\r\n");
+	for(i = 0; i < 4; i++) {
+		unsigned device;
+		device = ctrl->channel0[i];
+		if (device) {
+			int j;
+			print_debug("dimm: "); 
+			print_debug_hex8(i); 
+			print_debug(".0: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+		device = ctrl->channel1[i];
+		if (device) {
+			int j;
+			print_debug("dimm: "); 
+			print_debug_hex8(i); 
+			print_debug(".1: ");
+			print_debug_hex8(device);
+			for(j = 0; j < 256; j++) {
+				int status;
+				unsigned char byte;
+				if ((j & 0xf) == 0) {
+					print_debug("\r\n");
+					print_debug_hex8(j);
+					print_debug(": ");
+				}
+				status = smbus_read_byte(device, j);
+				if (status < 0) {
+					print_debug("bad device\r\n");
+					break;
+				}
+				byte = status & 0xff;
+				print_debug_hex8(byte);
+				print_debug_char(' ');
+			}
+			print_debug("\r\n");
+		}
+	}
+}
+static void dump_smbus_registers(void)
+{
+        int i;
+        print_debug("\r\n");
+        for(i = 1; i < 0x80; i++) {
+                unsigned device;
+                device = i;
+                int j;
+                print_debug("smbus: ");
+                print_debug_hex8(device);
+                for(j = 0; j < 256; j++) {
+                	int status; 
+                        unsigned char byte;
+                        if ((j & 0xf) == 0) {
+                	        print_debug("\r\n");
+                                print_debug_hex8(j);
+                                print_debug(": ");
+                        }
+                        status = smbus_read_byte(device, j);
+                        if (status < 0) {
+                                print_debug("bad device\r\n");
+                                break;
+                        }
+                        byte = status & 0xff;
+                        print_debug_hex8(byte);
+                        print_debug_char(' ');
+                }
+                print_debug("\r\n");
+	}	
+}
diff --git a/src/northbridge/transmeta/tm5800/northbridge.c b/src/northbridge/transmeta/tm5800/northbridge.c
new file mode 100644
index 0000000000..ccce795da4
--- /dev/null
+++ b/src/northbridge/transmeta/tm5800/northbridge.c
@@ -0,0 +1,131 @@
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <mem.h>
+#include <part/sizeram.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <device/chip.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include "chip.h"
+#include "northbridge.h"
+
+struct mem_range *sizeram(void)
+{
+	unsigned long mmio_basek;
+	static struct mem_range mem[10];
+	device_t dev;
+	int i, idx;
+
+#warning "FIXME handle interleaved nodes"
+	dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+	if (!dev) {
+		printk_err("Cannot find PCI: 0:18.1\n");
+		return 0;
+	}
+	mmio_basek = (dev_root.resource[1].base >> 10);
+	/* Round mmio_basek to something the processor can support */
+	mmio_basek &= ~((1 << 6) -1);
+
+#if 1
+#warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole"
+	/* Round the mmio hold to 256M */
+	mmio_basek &= ~((256*1024) - 1);
+#endif
+
+#if 0
+	printk_debug("mmio_base: %dKB\n", mmio_basek);
+#endif
+
+	for (idx = i = 0; i < 8; i++) {
+		uint32_t base, limit;
+		unsigned basek, limitk, sizek;
+		base  = pci_read_config32(dev, 0x40 + (i<<3));
+		limit = pci_read_config32(dev, 0x44 + (i<<3));
+		if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
+			continue;
+		}
+		basek = (base & 0xffff0000) >> 2;
+		limitk = ((limit + 0x00010000) & 0xffff0000) >> 2;
+		sizek = limitk - basek;
+		if ((idx > 0) &&
+		    ((mem[idx - 1].basek + mem[idx - 1].sizek) == basek)) {
+			mem[idx -1].sizek += sizek;
+		} else {
+			mem[idx].basek = basek;
+			mem[idx].sizek = sizek;
+			idx++;
+		}
+	
+		/* see if we need a hole from 0xa0000 to 0xbffff */
+		if ((mem[idx-1].basek < ((8*64)+(8*16))) /* 640 */ && 
+		    (mem[idx-1].sizek > ((8*64)+(16*16))) /* 768 */ ) {
+#warning "FIXME: this left 0xA0000 to 0xBFFFF undefined"
+			mem[idx].basek = (8*64)+(16*16);
+			mem[idx].sizek = mem[idx-1].sizek - ((8*64)+(16*16));
+			mem[idx-1].sizek = ((8*64)+(8*16)) - mem[idx-1].basek;
+			idx++;
+		}	
+		
+		/* See if I need to split the region to accomodate pci memory space */
+		if ((mem[idx - 1].basek <= mmio_basek) &&
+		    ((mem[idx - 1].basek + mem[idx - 1].sizek) >  mmio_basek)) {
+			if (mem[idx - 1].basek < mmio_basek) {
+				unsigned pre_sizek;
+				pre_sizek = mmio_basek - mem[idx - 1].basek;
+				mem[idx].basek = mmio_basek;
+				mem[idx].sizek = mem[idx - 1].sizek - pre_sizek;
+				mem[idx - 1].sizek = pre_sizek;
+				idx++;
+			}
+			if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
+				idx -= 1;
+			} else {
+				mem[idx - 1].basek = 4*1024*1024;
+				mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
+			}
+		}
+	}
+#if 1
+	for (i = 0; i < idx; i++) {
+		printk_debug("mem[%d].basek = %08x mem[%d].sizek = %08x\n",
+			     i, mem[i].basek, i, mem[i].sizek);
+	}
+#endif
+	while (idx < sizeof(mem)/sizeof(mem[0])) {
+		mem[idx].basek = 0;
+		mem[idx].sizek = 0;
+		idx++;
+	}
+	return mem;
+}
+
+static struct device_operations northbridge_operations = {
+	.read_resources   = tm5800_read_resources,
+	.set_resources    = tm5800_set_resources,
+	.enable_resources = tm5800_enable_resources,
+	.init             = mcf0_control_init,
+	.scan_bus         = tm5800_scan_chains,
+	.enable           = 0,
+};
+
+static struct pci_driver mcf0_driver __pci_driver = {
+	.ops    = &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_AMD,
+	.device = 0x1100,
+};
+
+static void enumerate(struct chip *chip)
+{
+	chip_enumerate(chip);
+	chip->dev->ops = &northbridge_operations;
+}
+
+struct chip_control northbridge_amd_tm5800_control = {
+	.name   = "Transmeta  tm5800 Northbridge",
+	.enumerate = enumerate,
+};
diff --git a/src/northbridge/transmeta/tm5800/northbridge.h b/src/northbridge/transmeta/tm5800/northbridge.h
new file mode 100644
index 0000000000..6d3b60f25b
--- /dev/null
+++ b/src/northbridge/transmeta/tm5800/northbridge.h
@@ -0,0 +1,5 @@
+#ifndef NORTHBRIDGE_AMD_AMDK8_H
+#define NORTHBRIDGE_AMD_AMDK8_H
+
+
+#endif /* NORTHBRIDGE_AMD_AMDK8_H */