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authorStefan Reinauer <stepan@coresystems.de>2009-10-26 17:12:21 +0000
committerStefan Reinauer <stepan@openbios.org>2009-10-26 17:12:21 +0000
commitaca6ec66bf7048e77ec960bb751a04e6b0528c70 (patch)
treef8fbc185686787e9453f0e6f229d88f38561333d /src/northbridge
parent3b314023802c7429012e5f09652047e0b32fb97a (diff)
downloadcoreboot-aca6ec66bf7048e77ec960bb751a04e6b0528c70.tar.xz
Kontron 986LCD-M update
- run ACPI code through preprocessor so we get the same values as the C code - fix PCIe x16 slot - fix ICH7 Azalia/HDA driver - SMI/GNVS update security fix (only allow struct pointer update once) - ACPI updates - IDE driver fixes - add cmos options for disabling onboard ethernet and controlling system fan Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/i945/acpi.c3
-rw-r--r--src/northbridge/intel/i945/acpi/i945.asl17
-rw-r--r--src/northbridge/intel/i945/acpi/i945_hostbridge.asl5
-rw-r--r--src/northbridge/intel/i945/early_init.c75
-rw-r--r--src/northbridge/intel/i945/i945.h18
-rw-r--r--src/northbridge/intel/i945/northbridge.c33
-rw-r--r--src/northbridge/intel/i945/raminit.c15
7 files changed, 128 insertions, 38 deletions
diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index 23aadd5752..2640cca3f6 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -27,6 +27,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include "i945.h"
unsigned long acpi_fill_mcfg(unsigned long current)
{
@@ -39,7 +40,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
if (!dev)
return current;
- pciexbar_reg=pci_read_config32(dev, 0x48);
+ pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 420ba0e592..9511925a69 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -19,7 +19,8 @@
* MA 02110-1301 USA
*/
-Include ("../../../northbridge/intel/i945/acpi/i945_hostbridge.asl")
+#include "../../../northbridge/intel/i945/acpi/i945_hostbridge.asl"
+#include "../../../northbridge/intel/i945/i945.h"
/* PCI Device Resource Consumption */
Device (PDRC)
@@ -41,10 +42,10 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
- Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
- Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
- Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
- Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
+ Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
+ Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
+ Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
@@ -76,13 +77,13 @@ Device (PDRC)
}
// PCIe graphics port 0:1.0
-Include ("../../../northbridge/intel/i945/acpi/i945_peg.asl")
+#include "../../../northbridge/intel/i945/acpi/i945_peg.asl"
// Integrated graphics 0:2.0
-Include ("../../../northbridge/intel/i945/acpi/i945_igd.asl")
+#include "../../../northbridge/intel/i945/acpi/i945_igd.asl"
Scope (\)
{
// backlight control, display switching, lid
- Include ("acpi/video.asl")
+ #include "acpi/video.asl"
}
diff --git a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
index 9e9c43611b..554adc0367 100644
--- a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
@@ -23,6 +23,9 @@
Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI
+Name(_ADR, 0)
+Name(_BBN, 0)
+
Device (MCHC)
{
Name(_ADR, 0x00000000) // 0:0.0
@@ -232,6 +235,6 @@ Method (_CRS, 0, Serialized)
}
/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
-Include ("acpi/i945_pci_irqs.asl")
+#include "acpi/i945_pci_irqs.asl"
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 5894bff5b1..e8dea60217 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -518,6 +518,33 @@ static void i945_setup_pci_express_x16(void)
reg32 &= ~(1 << 8);
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x208, reg32);
+ /* We have no success with querying the usual PCIe registers
+ * for link setup success on the i945. Hence we assign a temporary
+ * PCI bus 0x0a and check whether we find a device on 0:a.0
+ */
+
+ /* First we reset the secondary bus */
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+ reg16 |= (1 << 6);
+ pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+ /* Read back and clear reset bit. */
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e);
+ reg16 &= ~(1 << 6);
+ pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
+
+ reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
+ printk_debug("SLOTSTS: %04x\n", reg16);
+ if (!(reg16 & 0x48)) {
+ goto disable_pciexpress_x16_link;
+ }
+ reg16 |= (1 << 4) | (1 << 0);
+ pci_write_config16(PCI_DEV(0, 0x01, 0), 0xba, reg16);
+
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x00);
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x19, 0x0a);
+ pci_write_config8(PCI_DEV(0, 0x01, 0), 0x1a, 0x0a);
+
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x224);
reg32 &= ~(1 << 8);
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0x224, reg32);
@@ -542,11 +569,16 @@ static void i945_setup_pci_express_x16(void)
pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
/* Wait for training to succeed */
- printk_debug("Wait for PCIe x16 link training ...");
- timeout = 0x7fff;
+ printk_debug("PCIe link training ...");
+ timeout = 0x7ffff;
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
- if (!timeout) {
- printk_debug("timeout!\n");
+
+ reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
+ if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
+ printk_debug(" Detected PCIe device %04x:%04x\n",
+ reg32 & 0xffff, reg32 >> 16);
+ } else {
+ printk_debug(" timeout!\n");
printk_debug("Restrain PCIe port to x1\n");
@@ -562,18 +594,19 @@ static void i945_setup_pci_express_x16(void)
reg16 &= ~(1 << 6);
pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
- printk_debug("Wait for PCIe x1 link training ...");
- timeout = 0x7fff;
+ printk_debug("PCIe link training ...");
+ timeout = 0x7ffff;
while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ;
- if (!timeout) {
- printk_debug("timeout!\n");
+
+ reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
+ if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
+ printk_debug(" Detected PCIe x1 device %04x:%04x\n",
+ reg32 & 0xffff, reg32 >> 16);
+ } else {
+ printk_debug(" timeout!\n");
printk_debug("Disabling PCIe x16 port completely.\n");
goto disable_pciexpress_x16_link;
- } else {
- printk_debug("ok\n");
}
- } else {
- printk_debug("ok\n");
}
reg16 = pcie_read_config16(PCI_DEV(0, 0x01, 0), 0xb2);
@@ -592,6 +625,24 @@ static void i945_setup_pci_express_x16(void)
// TODO
}
+ reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
+ printk_debug("PCIe device class: %06x\n", reg32);
+ if (reg32 == 0x030000) {
+ printk_debug("PCIe device is VGA. Disabling IGD.\n");
+ reg16 = (1 << 1);
+ pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
+
+ /* DEVEN */
+ reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), 0x54);
+ reg32 &= ~((1 << 3) | (1 << 4));
+ pci_write_config32(PCI_DEV(0, 0x0, 0), 0x54, reg32);
+
+ /* Set VGA enable bit in PCIe bridge */
+ reg16 = pci_read_config16(PCI_DEV(0, 0x1, 0), 0x3e);
+ reg16 |= (1 << 3);
+ pci_write_config16(PCI_DEV(0, 0x1, 0), 0x3e, reg16);
+ }
+
/* Enable GPEs */
reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index a1f7185bde..a23e3a8f82 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -20,8 +20,18 @@
#ifndef __NORTHBRIDGE_INTEL_I945_I945_H__
#define __NORTHBRIDGE_INTEL_I945_I945_H__ 1
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#define DEFAULT_X60BAR 0xfed13000
+#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
+#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
+
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
/* Device 0:0.0 PCI configuration space (Host Bridge) */
#define EPBAR 0x40
@@ -30,13 +40,6 @@
#define DMIBAR 0x4c
#define X60BAR 0x60
-/* Northbridge BARs */
-#define DEFAULT_PCIEXBAR 0xf0000000 /* 4 KB per PCIe device */
-#define DEFAULT_X60BAR 0xfed13000
-#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
-#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
-#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-
#define GGC 0x52 /* GMCH Graphics Control */
#define DEVEN 0x54 /* Device Enable */
@@ -329,3 +332,4 @@
#define DMIDRCCFG 0xeb4 /* 32bit */
#endif
+#endif
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index b2851cd336..4ccffc6b55 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -44,7 +44,7 @@ int get_pcie_bar(u32 *base, u32 *len)
if (!dev)
return 0;
- pciexbar_reg = pci_read_config32(dev, 0x48);
+ pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
@@ -67,9 +67,6 @@ int get_pcie_bar(u32 *base, u32 *len)
return 0;
}
-/* in arch/i386/boot/tables.c */
-extern uint64_t high_tables_base, high_tables_size;
-
/* IDG memory */
uint64_t uma_memory_base=0, uma_memory_size=0;
@@ -127,7 +124,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
}
#if CONFIG_WRITE_HIGH_TABLES==1
-#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
+#define HIGH_TABLES_SIZE 1024 // maximum size of high tables in KB
extern uint64_t high_tables_base, high_tables_size;
#endif
@@ -284,6 +281,28 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
}
}
+#if CONFIG_HAVE_ACPI_RESUME
+extern u8 acpi_slp_type;
+
+static void northbridge_init(struct device *dev)
+{
+ switch (pci_read_config32(dev, SKPAD)) {
+ case 0xcafebabe:
+ printk_debug("Normal boot.\n");
+ acpi_slp_type=0;
+ break;
+ case 0xcafed00d:
+ printk_debug("S3 Resume.\n");
+ acpi_slp_type=3;
+ break;
+ default:
+ printk_debug("Unknown boot method, assuming normal.\n");
+ acpi_slp_type=0;
+ break;
+ }
+}
+#endif
+
static struct pci_operations intel_pci_ops = {
.set_subsystem = intel_set_subsystem,
};
@@ -292,7 +311,9 @@ static struct device_operations mc_ops = {
.read_resources = mc_read_resources,
.set_resources = mc_set_resources,
.enable_resources = pci_dev_enable_resources,
- .init = 0,
+#if CONFIG_HAVE_ACPI_RESUME
+ .init = northbridge_init,
+#endif
.scan_bus = 0,
.ops_pci = &intel_pci_ops,
};
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 3084072389..53a7455ea9 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2481,6 +2481,9 @@ static void sdram_program_receive_enable(struct sys_info *sysinfo)
{
MCHBAR32(REPC) |= (1 << 0);
+ /* enable upper CMOS */
+ RCBA32(0x3400) = (1 << 2);
+
/* Program Receive Enable Timings */
if (sysinfo->boot_path == BOOT_PATH_RESUME) {
sdram_recover_receive_enable();
@@ -2904,9 +2907,7 @@ void sdram_initialize(int boot_path)
sdram_thermal_management();
/* Normal Operations */
- if (boot_path == BOOT_PATH_NORMAL) {
- sdram_init_complete();
- }
+ sdram_init_complete();
/* Program Receive Enable Timings */
sdram_program_receive_enable(&sysinfo);
@@ -2924,3 +2925,11 @@ void sdram_initialize(int boot_path)
sdram_setup_processor_side();
}
+unsigned long get_top_of_ram(void)
+{
+ /* This will not work if TSEG is in place! */
+ u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
+
+ return (unsigned long) tom;
+}
+