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| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-04-10 15:16:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-23 14:47:53 +0000 |
| commit | c82950bf79285fa838b6fbaf019a5638316ba053 (patch) | |
| tree | 3f344f1d85367986ee0e635b724d9e6ff3a23589 /src/northbridge | |
| parent | f26693283655eff7c31275621439f8416eeb3242 (diff) | |
| download | coreboot-c82950bf79285fa838b6fbaf019a5638316ba053.tar.xz | |
nb/intel/x4x: Use parallel MP init
Use parallel MP init code to initialize all AP's.
Also remove guards around CPU code where all platforms now use
parallel MP init.
This also removes the code required on lapic init path for
model_6fx, model_1017x and model_f4x as all platforms now use the
parallel MP code.
Tested on Intel DG41WV, shaves off about 90ms on a quad core.
Change-Id: Id5a2729f5bf6b525abad577e63d7953ae6640921
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/x4x/Kconfig | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/northbridge.c | 22 |
2 files changed, 2 insertions, 21 deletions
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 117ac03882..6f3546f7f4 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -29,6 +29,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select POSTCAR_STAGE select POSTCAR_CONSOLE select SMM_TSEG + select PARALLEL_MP config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 7de39d1672..4b5a754a1c 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -182,26 +182,6 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, D0F0_SMRAM, smram); } -/* - * Really doesn't belong here but will go away with parallel mp init, - * so let it be here for a while... - */ -int cpu_get_apic_id_map(int *apic_id_map) -{ - unsigned int i; - - /* Logical processors (threads) per core */ - const struct cpuid_result cpuid1 = cpuid(1); - /* Read number of cores. */ - const char cores = (cpuid1.ebx >> 16) & 0xf; - - /* TODO in parallel MP cpuid(1).ebx */ - for (i = 0; i < cores; i++) - apic_id_map[i] = i; - - return cores; -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -215,7 +195,7 @@ static struct device_operations pci_domain_ops = { static void cpu_bus_init(struct device *dev) { - initialize_cpus(dev->link_list); + bsp_init_and_start_aps(dev->link_list); } static struct device_operations cpu_bus_ops = { |