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| author | Patrick Georgi <patrick@georgi-clan.de> | 2014-08-10 15:19:45 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2014-11-28 17:56:29 +0100 |
| commit | d3060edce222a372e3935ff6c270479815aafbe4 (patch) | |
| tree | b29db0b8ed06f85a27f75bf06d786088906e3ffe /src/northbridge | |
| parent | 24d875bddc5812b3b9041f557019fea14a71ebe7 (diff) | |
| download | coreboot-d3060edce222a372e3935ff6c270479815aafbe4.tar.xz | |
i945: make PCIe link wait sensible
Waiting for (a & 4) == 3 to become true proves futile
unless you're searching for defective hardware or
neutrino impact.
While I'm not 100% sure that this is the actual intent
(no data-sheets at hand, and the public ones are unhelpful
as usual), it's the likely correct version and it's also
boot-tested on intel/d945gclf.
While at it, replace register number with the name found
in the public datasheet.
Change-Id: I4b87001967a2013e0089806e8cd606d5ee81b0d9
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6575
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/i945/i945.h | 1 |
2 files changed, 6 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1715c476ad..f639aef146 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -588,7 +588,7 @@ static void i945_setup_pci_express_x16(void) /* Wait for training to succeed */ printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ; reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -599,10 +599,10 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "Restrain PCIe port to x1\n"); - reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); reg32 &= ~(0xf << 1); reg32 |=1; - pci_write_config32(PCI_DEV(0, 0x01, 0), 0x214, reg32); + pci_write_config32(PCI_DEV(0, 0x01, 0), PEGSTS, reg32); reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0x3e); @@ -613,7 +613,7 @@ static void i945_setup_pci_express_x16(void) printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; - while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3) && --timeout) ; + while ((((pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS) >> 16) & 3) != 3) && --timeout) ; reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0); if (reg32 != 0x00000000 && reg32 != 0xffffffff) { @@ -787,7 +787,7 @@ disable_pciexpress_x16_link: printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; - for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x214); + for (reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), PEGSTS); (reg32 & 0x000f0000) && --timeout;) ; if (!timeout) printk(BIOS_DEBUG, "timeout!\n"); diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 8573b0c261..fe59ebe9b7 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -83,6 +83,7 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ #define BCTRL1 0x3e /* 16bit */ +#define PEGSTS 0x214 /* 32bit */ /* Device 0:2.0 PCI configuration space (Graphics Device) */ |