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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-05-26 10:12:45 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2015-05-27 12:50:53 +0200
commitf7284089e3657c66efeeb180a1f101a60d832901 (patch)
treecb16884784c2623d06b85d91bb14dbf5b0899153 /src/northbridge
parent49d30668b628cb68c61a7b2512628263752360c3 (diff)
downloadcoreboot-f7284089e3657c66efeeb180a1f101a60d832901.tar.xz
AGESA: Split S3 backup in CBMEM
Use separate CBMEM allocations for stack and heap on S3 resume path. The allocation of HIGH_SCRATCH_MEMORY is specific to AGESA and is moved out of globals and ACPI. This region is a replacement for BIOS_HEAP_SIZE used on non-resume paths. Change-Id: I6658ce1c06964de5cf13b4e3c84d571f46ce76f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10316 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/agesa/BiosCallOuts.h2
-rw-r--r--src/northbridge/amd/agesa/oem_s3.c7
2 files changed, 7 insertions, 2 deletions
diff --git a/src/northbridge/amd/agesa/BiosCallOuts.h b/src/northbridge/amd/agesa/BiosCallOuts.h
index 64f1cd5e9e..cfe1852fd4 100644
--- a/src/northbridge/amd/agesa/BiosCallOuts.h
+++ b/src/northbridge/amd/agesa/BiosCallOuts.h
@@ -30,13 +30,11 @@
#define BIOS_HEAP_START_ADDRESS 0x010000000
#define BIOS_HEAP_SIZE 0x30000
-#define BSP_STACK_BASE_ADDR 0x30000
#else
#define BIOS_HEAP_START_ADDRESS 0x10000 /* HEAP during cold boot */
#define BIOS_HEAP_SIZE 0x20000
-#define BSP_STACK_BASE_ADDR 0x30000
#endif
diff --git a/src/northbridge/amd/agesa/oem_s3.c b/src/northbridge/amd/agesa/oem_s3.c
index 08f68e58b4..779e28b553 100644
--- a/src/northbridge/amd/agesa/oem_s3.c
+++ b/src/northbridge/amd/agesa/oem_s3.c
@@ -20,6 +20,7 @@
#include <spi-generic.h>
#include <spi_flash.h>
#include <string.h>
+#include <cbmem.h>
#include <cpu/amd/agesa/s3_resume.h>
#include <northbridge/amd/agesa/BiosCallOuts.h>
#include <northbridge/amd/agesa/agesawrapper.h>
@@ -133,6 +134,12 @@ AGESA_STATUS OemS3Save(AMD_S3SAVE_PARAMS *S3SaveParams)
u32 MTRRStorageSize = 0;
u32 pos, size;
+ if (HIGH_ROMSTAGE_STACK_SIZE)
+ cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE);
+
+ if (HIGH_MEMORY_SCRATCH)
+ cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH);
+
/* To be consumed in AmdInitResume. */
get_s3nv_data(S3DataTypeNonVolatile, &pos, &size);
if (size && dataBlock->NvStorageSize)