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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-04-08 14:31:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-11 17:56:57 +0200 |
| commit | 064a50160a55058a7baa00a91cbb9ceb0126cda6 (patch) | |
| tree | 41c0933eaba8bbc10bee2df7562a1b01656d3712 /src/northbridge | |
| parent | 54e055179dd19307a8e8ac2c94b224ebe988ed5d (diff) | |
| download | coreboot-064a50160a55058a7baa00a91cbb9ceb0126cda6.tar.xz | |
cpu/x86/tsc: Compile TSC timer for postcar as well
Change-Id: I8fd79d438756aae03649e320d4d640cee284d88a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge')
0 files changed, 0 insertions, 0 deletions