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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-08-08 20:29:55 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-22 23:10:12 +0100
commit0d2fdeb36afdd3cfd7576b4c2fb79e134bb58630 (patch)
tree0204dfb1a2980c910dfb8bd7052863d665dd59ff /src/northbridge
parenteb295a3e69483aab2ee4ce1231f1e2e6c6cd9982 (diff)
downloadcoreboot-0d2fdeb36afdd3cfd7576b4c2fb79e134bb58630.tar.xz
amd/amdmct/mct_ddr3: Set prefetch double stride to improve performance
Change-Id: I34ad85388c6b71f0d44bee13afd663e0b84545cd Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12037 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mct_d.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 4b4a0381a5..d76eea0e2a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -5313,6 +5313,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */
val |= (0x1 << 8);
val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */
+ val |= (0x1 << 20); /* DblPrefEn = 0x1 */
val |= (0x7 << 22); /* PrefFourConf = 0x7 */
val |= (0x7 << 25); /* PrefFiveConf = 0x7 */
val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */