Uniformly spell frequency unit symbol as Hz

Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

26 files changed, 169 insertions, 169 deletions

diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c
index 55da604551..764d2988b4 100644
--- a/src/northbridge/amd/amdht/h3finit.c
+++ b/src/northbridge/amd/amdht/h3finit.c
@@ -1518,7 +1518,7 @@ static void hammerSublinkFixup(sMainData *pDat)
 				{
 					if ((loFreq != 5) &&  /* { 9, 5} 1600MHz /  800MHz 2:1 */
 						(loFreq != 2) &&  /* { 9, 2} 1600MHz /  400MHz 4:1 */
-						(loFreq != 0) )   /* { 9, 0} 1600MHz /  200Mhz 8:1 */
+						(loFreq != 0) )   /* { 9, 0} 1600MHz /  200MHz 8:1 */
 						downgrade = TRUE;
 				}
 				else if (hiFreq == 7)
diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c
index 830ed1cc22..e83f872bc0 100644
--- a/src/northbridge/amd/amdht/h3ncmn.c
+++ b/src/northbridge/amd/amdht/h3ncmn.c
@@ -1384,7 +1384,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
 			ASSERT((temp >= HT_FREQUENCY_600M && temp <= HT_FREQUENCY_2600M)
 				|| (temp == HT_FREQUENCY_200M) || (temp == HT_FREQUENCY_400M));
 			AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp);
-			if (temp > HT_FREQUENCY_1000M) /*  Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */
+			if (temp > HT_FREQUENCY_1000M) /*  Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz */
 			{
 				/* Enable  for Gen3 frequencies */
 				temp = 1;
@@ -1420,7 +1420,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb)
 
 			/* Handle additional HT3 frequency requirements, if needed,
 			 * or clear them if switching down to ht1 on a warm reset.
-			 * Gen1 = 200Mhz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
+			 * Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 2600MHz
 			 *
 			 * Even though we assert if debugging, we need to check that the capability was found
 			 * always, since this is an unknown hardware device, also we are taking
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 5219d4c20e..8abb31fad0 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -295,7 +295,7 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos)
 
 	id = pci_read_config32(dev, 0);
 
-	/* AMD K8 Unsupported 1Ghz? */
+	/* AMD K8 Unsupported 1GHz? */
 	if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
 		freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 	}
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index 9d92174855..cf8ad52fba 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -135,7 +135,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos)
 		return freq_cap;
 	}
 
-	/* AMD K8 Unsupported 1Ghz? */
+	/* AMD K8 Unsupported 1GHz? */
 	if (id == (PCI_VENDOR_ID_AMD | (0x1100 << 16))) {
 	#if CONFIG_K8_HT_FREQ_1G_SUPPORT
 		#if !CONFIG_K8_REV_F_SUPPORT
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index f3194503a9..19f83b998e 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -284,14 +284,14 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	 *	   111 = reserved
 	 * [ 7: 7] Reserved
 	 * [12: 8] Tref (Refresh Rate)
-	 *	   00000 = 100Mhz 4K rows
-	 *	   00001 = 133Mhz 4K rows
-	 *	   00010 = 166Mhz 4K rows
-	 *	   00011 = 200Mhz 4K rows
-	 *	   01000 = 100Mhz 8K/16K rows
-	 *	   01001 = 133Mhz 8K/16K rows
-	 *	   01010 = 166Mhz 8K/16K rows
-	 *	   01011 = 200Mhz 8K/16K rows
+	 *	   00000 = 100MHz 4K rows
+	 *	   00001 = 133MHz 4K rows
+	 *	   00010 = 166MHz 4K rows
+	 *	   00011 = 200MHz 4K rows
+	 *	   01000 = 100MHz 8K/16K rows
+	 *	   01001 = 133MHz 8K/16K rows
+	 *	   01010 = 166MHz 8K/16K rows
+	 *	   01011 = 200MHz 8K/16K rows
 	 * [19:13] Reserved
 	 * [22:20] Twcl (Write CAS Latency)
 	 *	   000 = 1 Mem clock after CAS# (Unbuffered Dimms)
@@ -414,12 +414,12 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
 	 *	   0 = Use Idle Cycle Limit
 	 *	   1 = Generate a dynamic Idle cycle limit
 	 * [22:20] DRAM MEMCLK Frequency
-	 *	   000 = 100Mhz
+	 *	   000 = 100MHz
 	 *	   001 = reserved
-	 *	   010 = 133Mhz
+	 *	   010 = 133MHz
 	 *	   011 = reserved
 	 *	   100 = reserved
-	 *	   101 = 166Mhz
+	 *	   101 = 166MHz
 	 *	   110 = reserved
 	 *	   111 = reserved
 	 * [24:23] Reserved
diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h
index a8f7d70ca8..da0d01b093 100644
--- a/src/northbridge/amd/amdmct/mct/mct.h
+++ b/src/northbridge/amd/amdmct/mct/mct.h
@@ -28,8 +28,8 @@
 
 #define J_MIN		0		/* j loop constraint. 1=CL 2.0 T*/
 #define J_MAX		4		/* j loop constraint. 4=CL 6.0 T*/
-#define K_MIN		1		/* k loop constraint. 1=200 Mhz*/
-#define K_MAX		4		/* k loop constraint. 9=400 Mhz*/
+#define K_MIN		1		/* k loop constraint. 1=200 MHz*/
+#define K_MAX		4		/* k loop constraint. 9=400 MHz*/
 #define CL_DEF		2		/* Default value for failsafe operation. 2=CL 4.0 T*/
 #define T_DEF		1		/* Default value for failsafe operation. 1=5ns (cycle time)*/
 
@@ -236,10 +236,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 DATAload[2];		/* Number of ranks loading CH A DATA*/
 					/* Number of ranks loading CH B DATA*/
 	u8 DIMMAutoSpeed;		/* Max valid Mfg. Speed of DIMMs
-					   1=200Mhz
-					   2=266Mhz
-					   3=333Mhz
-					   4=400Mhz */
+					   1=200MHz
+					   2=266MHz
+					   3=333MHz
+					   4=400MHz */
 	u8 DIMMCASL;		/* Min valid Mfg. CL bitfield
 					   0=2.0
 					   1=3.0
@@ -255,10 +255,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u16 DIMMTrrd;	/* Minimax Trrd*40 (ns) of DIMMs*/
 	u16 DIMMTwtr;	/* Minimax Twtr*40 (ns) of DIMMs*/
 	u8 Speed;		/* Bus Speed (to set Controller)
-				   1=200Mhz
-				   2=266Mhz
-				   3=333Mhz
-				   4=400Mhz */
+				   1=200MHz
+				   2=266MHz
+				   3=333MHz
+				   4=400MHz */
 	u8 CASL;		/* CAS latency DCT setting
 				   0=2.0
 				   1=3.0
@@ -288,10 +288,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 DCTHoleBase;	/* If not zero, BASE[39:8] (system address) of dram hole for HW remapping.  Dram hole exists on this Node's DCTs. */
 	u32 DCTSysLimit;	/* LIMIT[39:8] (system address) of this Node's DCTs */
 	u16 PresetmaxFreq;	/* Maximum OEM defined DDR frequency
-				   200=200Mhz (DDR400)
-				   266=266Mhz (DDR533)
-				   333=333Mhz (DDR667)
-				   400=400Mhz (DDR800) */
+				   200=200MHz (DDR400)
+				   266=266MHz (DDR533)
+				   333=333MHz (DDR667)
+				   400=400MHz (DDR800) */
 	u8 _2Tmode;	/* 1T or 2T CMD mode (slow access mode)
 				   1=1T
 				   2=2T */
@@ -408,10 +408,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 #define NV_MAX_NODES		1	/* Number of Nodes/Sockets (4-bits)*/
 #define NV_MAX_DIMMS		2	/* Number of DIMM slots for the specified Node ID (4-bits)*/
 #define NV_MAX_MEMCLK		3	/* Maximum platform demonstrated Memclock (10-bits)
-					   200=200Mhz (DDR400)
-					   266=266Mhz (DDR533)
-					   333=333Mhz (DDR667)
-					   400=400Mhz (DDR800)*/
+					   200=200MHz (DDR400)
+					   266=266MHz (DDR533)
+					   333=333MHz (DDR667)
+					   400=400MHz (DDR800)*/
 #define NV_ECC_CAP		4	/* Bus ECC capable (1-bits)
 					   0=Platform not capable
 					   1=Platform is capable*/
@@ -433,10 +433,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 					   1=Auto, user limit provided in NV_MemCkVal
 					   2=Manual, user value provided in NV_MemCkVal*/
 #define NV_MemCkVal		11	/* Memory Clock Value (2-bits)
-					   0=200Mhz
-					   1=266Mhz
-					   2=333Mhz
-					   3=400Mhz*/
+					   0=200MHz
+					   1=266MHz
+					   2=333MHz
+					   3=400MHz*/
 
 /* Dram Configuration */
 #define NV_BankIntlv		20	/* Dram Bank (chip-select) Interleaving (1-bits)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 66eb88a7e9..924c5fb645 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -203,7 +203,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 *     entry
 	 * 6. All var MTRRs reset to zero
 	 * 7. State of NB_CFG.DisDatMsk set properly on all CPUs
-	 * 8. All CPUs at 2Ghz Speed (unless DQS training is not installed).
+	 * 8. All CPUs at 2GHz Speed (unless DQS training is not installed).
 	 * 9. All cHT links at max Speed/Width (unless DQS training is not
 	 *     installed).
 	 *
@@ -212,11 +212,11 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * j CL(j)       k   F(k)
 	 * --------------------------
 	 * 0 2.0         -   -
-	 * 1 3.0         1   200 Mhz
-	 * 2 4.0         2   266 Mhz
-	 * 3 5.0         3   333 Mhz
-	 * 4 6.0         4   400 Mhz
-	 * 5 7.0         5   533 Mhz
+	 * 1 3.0         1   200 MHz
+	 * 2 4.0         2   266 MHz
+	 * 3 5.0         3   333 MHz
+	 * 4 6.0         4   400 MHz
+	 * 5 7.0         5   533 MHz
 	 */
 	u8 Node, NodesWmem;
 	u32 node_sys_base;
@@ -437,9 +437,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				 * when 400, 533, 667, it will support dimm0/1/2/3,
 				 * and set conf for dimm0, hw will copy to dimm1/2/3
 				 * set for dimm1, hw will copy to dimm3
-				 * Rev A/B only support DIMM0/1 when 800Mhz and above
+				 * Rev A/B only support DIMM0/1 when 800MHz and above
 				 *   + 0x100 to next dimm
-				 * Rev C support DIMM0/1/2/3 when 800Mhz and above
+				 * Rev C support DIMM0/1/2/3 when 800MHz and above
 				 *   + 0x100 to next dimm
 				*/
 				for (DIMM = 0; DIMM < 2; DIMM++) {
@@ -3615,7 +3615,7 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
 	u32 dev = pDCTstat->dev_dct;
 
 	// FIXME: skip for Ax
-	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533Mhz
+	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
 		for (i=0; i < 2; i++) {
 			reg_off = 0x100 * i;
 			Set_NB32(dev,  0x98 + reg_off, 0x0D000030);
@@ -3630,7 +3630,7 @@ static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
 			struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
 {
 	// FIXME: Skip for Ax
-	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533Mhz
+	if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
 		*dqs_pos = 32;
 	}
 }
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index 4370b8da96..0a1f925291 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -35,8 +35,8 @@
 
 #define J_MIN		0		/* j loop constraint. 1=CL 2.0 T*/
 #define J_MAX		5		/* j loop constraint. 5=CL 7.0 T*/
-#define K_MIN		1		/* k loop constraint. 1=200 Mhz*/
-#define K_MAX		5		/* k loop constraint. 5=533 Mhz*/
+#define K_MIN		1		/* k loop constraint. 1=200 MHz*/
+#define K_MAX		5		/* k loop constraint. 5=533 MHz*/
 #define CL_DEF		2		/* Default value for failsafe operation. 2=CL 4.0 T*/
 #define T_DEF		1		/* Default value for failsafe operation. 1=5ns (cycle time)*/
 
@@ -325,11 +325,11 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 DATAload[2];		/*Number of ranks loading CH A DATA*/
 		/* Number of ranks loading CH B DATA*/
 	u8 DIMMAutoSpeed;	/*Max valid Mfg. Speed of DIMMs
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz
-		5=533Mhz*/
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz
+		5=533MHz*/
 	u8 DIMMCASL;		/* Min valid Mfg. CL bitfield
 		0=2.0
 		1=3.0
@@ -345,10 +345,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u16 DIMMTrrd;		/* Minimax Trrd*40 (ns) of DIMMs*/
 	u16 DIMMTwtr;		/* Minimax Twtr*40 (ns) of DIMMs*/
 	u8 Speed;		/* Bus Speed (to set Controller)
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz */
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz */
 	u8 CASL;		/* CAS latency DCT setting
 		0=2.0
 		1=3.0
@@ -378,10 +378,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 DCTHoleBase;	/* If not zero, BASE[39:8] (system address) of dram hole for HW remapping.  Dram hole exists on this Node's DCTs. */
 	u32 DCTSysLimit;	/* LIMIT[39:8] (system address) of this Node's DCTs */
 	u16 PresetmaxFreq;	/* Maximum OEM defined DDR frequency
-		200=200Mhz (DDR400)
-		266=266Mhz (DDR533)
-		333=333Mhz (DDR667)
-		400=400Mhz (DDR800) */
+		200=200MHz (DDR400)
+		266=266MHz (DDR533)
+		333=333MHz (DDR667)
+		400=400MHz (DDR800) */
 	u8 _2Tmode;		/* 1T or 2T CMD mode (slow access mode)
 		1=1T
 		2=2T */
@@ -476,9 +476,9 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 WrDatGrossH;
 	u8 DqsRcvEnGrossL;
 	// NOTE: Not used - u8 NodeSpeed		/* Bus Speed (to set Controller)
-		/* 1=200Mhz */
-		/* 2=266Mhz */
-		/* 3=333Mhz */
+		/* 1=200MHz */
+		/* 2=266MHz */
+		/* 3=333MHz */
 	// NOTE: Not used - u8 NodeCASL		/* CAS latency DCT setting
 		/* 0=2.0 */
 		/* 1=3.0 */
@@ -574,10 +574,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 #define NV_MAX_NODES		1	/* Number of Nodes/Sockets (4-bits)*/
 #define NV_MAX_DIMMS		2	/* Number of DIMM slots for the specified Node ID (4-bits)*/
 #define NV_MAX_MEMCLK		3	/* Maximum platform demonstrated Memclock (10-bits)
-					    200=200Mhz (DDR400)
-					    266=266Mhz (DDR533)
-					    333=333Mhz (DDR667)
-					    400=400Mhz (DDR800)*/
+					    200=200MHz (DDR400)
+					    266=266MHz (DDR533)
+					    333=333MHz (DDR667)
+					    400=400MHz (DDR800)*/
 #define NV_ECC_CAP		4	/* Bus ECC capable (1-bits)
 					    0=Platform not capable
 					    1=Platform is capable*/
@@ -599,10 +599,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 					    1=Auto, user limit provided in NV_MemCkVal
 					    2=Manual, user value provided in NV_MemCkVal*/
 #define NV_MemCkVal		11	/* Memory Clock Value (2-bits)
-					    0=200Mhz
-					    1=266Mhz
-					    2=333Mhz
-					    3=400Mhz*/
+					    0=200MHz
+					    1=266MHz
+					    2=333MHz
+					    3=400MHz*/
 
 /*Dram Configuration*/
 #define NV_BankIntlv		20	/* Dram Bank (chip-select) Interleaving (1-bits)
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index ab1347a9f8..17fb289268 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -591,8 +591,8 @@ void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
@@ -615,8 +615,8 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index 529a7366eb..ab6f9ce0c0 100644
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -290,7 +290,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct)
 	tmp = pDCTstat->LogicalCPUID;
 	if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
 		Speed = pDCTstat->Speed;
-		/* MemClkFreq = 333MHz or 533Mhz */
+		/* MemClkFreq = 333MHz or 533MHz */
 		if((Speed == 3) || (Speed == 2)) {
 			if(pDCTstat->GangedMode) {
 				ch_start = 0;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 90b7ed33ec..770b663fe9 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -248,7 +248,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
 	 * 6. All var MTRRs reset to zero
 	 * 7. State of NB_CFG.DisDatMsk set properly on all CPUs
-	 * 8. All CPUs at 2Ghz Speed (unless DQS training is not installed).
+	 * 8. All CPUs at 2GHz Speed (unless DQS training is not installed).
 	 * 9. All cHT links at max Speed/Width (unless DQS training is not installed).
 	 *
 	 *
@@ -258,13 +258,13 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
 	 * j CL(j)       k   F(k)
 	 * --------------------------
 	 * 0 2.0         -   -
-	 * 1 3.0         1   200 Mhz
-	 * 2 4.0         2   266 Mhz
-	 * 3 5.0         3   333 Mhz
-	 * 4 6.0         4   400 Mhz
-	 * 5 7.0         5   533 Mhz
-	 * 6 8.0         6   667 Mhz
-	 * 7 9.0         7   800 Mhz
+	 * 1 3.0         1   200 MHz
+	 * 2 4.0         2   266 MHz
+	 * 3 5.0         3   333 MHz
+	 * 4 6.0         4   400 MHz
+	 * 5 7.0         5   533 MHz
+	 * 6 8.0         6   667 MHz
+	 * 7 9.0         7   800 MHz
 	 */
 	u8 Node, NodesWmem;
 	u32 node_sys_base;
@@ -487,9 +487,9 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
 				 * when 400, 533, 667, it will support dimm0/1/2/3,
 				 * and set conf for dimm0, hw will copy to dimm1/2/3
 				 * set for dimm1, hw will copy to dimm3
-				 * Rev A/B only support DIMM0/1 when 800Mhz and above
+				 * Rev A/B only support DIMM0/1 when 800MHz and above
 				 *   + 0x100 to next dimm
-				 * Rev C support DIMM0/1/2/3 when 800Mhz and above
+				 * Rev C support DIMM0/1/2/3 when 800MHz and above
 				 *   + 0x100 to next dimm
 				*/
 				for (DIMM = 0; DIMM < 4; DIMM++) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index d2872e439c..42cca2640b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -35,8 +35,8 @@
 
 #define J_MIN		0		/* j loop constraint. 1=CL 2.0 T*/
 #define J_MAX		5		/* j loop constraint. 5=CL 7.0 T*/
-#define K_MIN		1		/* k loop constraint. 1=200 Mhz*/
-#define K_MAX		5		/* k loop constraint. 5=533 Mhz*/
+#define K_MIN		1		/* k loop constraint. 1=200 MHz*/
+#define K_MAX		5		/* k loop constraint. 5=533 MHz*/
 #define CL_DEF		2		/* Default value for failsafe operation. 2=CL 4.0 T*/
 #define T_DEF		1		/* Default value for failsafe operation. 1=5ns (cycle time)*/
 
@@ -352,11 +352,11 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 DATAload[2];		/*Number of ranks loading CH A DATA*/
 		/* Number of ranks loading CH B DATA*/
 	u8 DIMMAutoSpeed;	/*Max valid Mfg. Speed of DIMMs
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz
-		5=533Mhz*/
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz
+		5=533MHz*/
 	u8 DIMMCASL;		/* Min valid Mfg. CL bitfield
 		0=2.0
 		1=3.0
@@ -372,10 +372,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u16 DIMMTrrd;		/* Minimax Trrd*40 (ns) of DIMMs*/
 	u16 DIMMTwtr;		/* Minimax Twtr*40 (ns) of DIMMs*/
 	u8 Speed;		/* Bus Speed (to set Controller)
-		1=200Mhz
-		2=266Mhz
-		3=333Mhz
-		4=400Mhz */
+		1=200MHz
+		2=266MHz
+		3=333MHz
+		4=400MHz */
 	u8 CASL;		/* CAS latency DCT setting
 		0=2.0
 		1=3.0
@@ -405,10 +405,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u32 DCTHoleBase;	/* If not zero, BASE[39:8] (system address) of dram hole for HW remapping.  Dram hole exists on this Node's DCTs. */
 	u32 DCTSysLimit;	/* LIMIT[39:8] (system address) of this Node's DCTs */
 	u16 PresetmaxFreq;	/* Maximum OEM defined DDR frequency
-		200=200Mhz (DDR400)
-		266=266Mhz (DDR533)
-		333=333Mhz (DDR667)
-		400=400Mhz (DDR800) */
+		200=200MHz (DDR400)
+		266=266MHz (DDR533)
+		333=333MHz (DDR667)
+		400=400MHz (DDR800) */
 	u8 _2Tmode;		/* 1T or 2T CMD mode (slow access mode)
 		1=1T
 		2=2T */
@@ -518,9 +518,9 @@ struct DCTStatStruc {		/* A per Node structure*/
 	u8 WrDatGrossH;
 	u8 DqsRcvEnGrossL;
 	/* NOTE: Not used - u8 NodeSpeed */		/* Bus Speed (to set Controller) */
-		/* 1=200Mhz */
-		/* 2=266Mhz */
-		/* 3=333Mhz */
+		/* 1=200MHz */
+		/* 2=266MHz */
+		/* 3=333MHz */
 	/* NOTE: Not used - u8 NodeCASL	*/	/* CAS latency DCT setting */
 		/* 0=2.0 */
 		/* 1=3.0 */
@@ -635,10 +635,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 #define NV_MAX_NODES		1	/* Number of Nodes/Sockets (4-bits)*/
 #define NV_MAX_DIMMS		2	/* Number of DIMM slots for the specified Node ID (4-bits)*/
 #define NV_MAX_MEMCLK		3	/* Maximum platform demonstrated Memclock (10-bits)
-					    200=200Mhz (DDR400)
-					    266=266Mhz (DDR533)
-					    333=333Mhz (DDR667)
-					    400=400Mhz (DDR800)*/
+					    200=200MHz (DDR400)
+					    266=266MHz (DDR533)
+					    333=333MHz (DDR667)
+					    400=400MHz (DDR800)*/
 #define NV_ECC_CAP		4	/* Bus ECC capable (1-bits)
 					    0=Platform not capable
 					    1=Platform is capable*/
@@ -660,10 +660,10 @@ struct DCTStatStruc {		/* A per Node structure*/
 					    1=Auto, user limit provided in NV_MemCkVal
 					    2=Manual, user value provided in NV_MemCkVal*/
 #define NV_MemCkVal		11	/* Memory Clock Value (2-bits)
-					    0=200Mhz
-					    1=266Mhz
-					    2=333Mhz
-					    3=400Mhz*/
+					    0=200MHz
+					    1=266MHz
+					    2=333MHz
+					    3=400MHz*/
 
 /*Dram Configuration*/
 #define NV_BankIntlv		20	/* Dram Bank (chip-select) Interleaving (1-bits)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 76d01dadb2..d7084ad385 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -668,8 +668,8 @@ static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
@@ -709,8 +709,8 @@ static void GetDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat,
 	/* When 400, 533, 667, it will support dimm0/1/2/3,
 	 * and set conf for dimm0, hw will copy to dimm1/2/3
 	 * set for dimm1, hw will copy to dimm3
-	 * Rev A/B only support DIMM0/1 when 800Mhz and above + 0x100 to next dimm
-	 * Rev C support DIMM0/1/2/3 when 800Mhz and above  + 0x100 to next dimm
+	 * Rev A/B only support DIMM0/1 when 800MHz and above + 0x100 to next dimm
+	 * Rev C support DIMM0/1/2/3 when 800MHz and above  + 0x100 to next dimm
 	 */
 
 	/* FindDQSDatDimmVal_D is not required since we use an array */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 1446f4ff6b..80557fdf69 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -741,7 +741,7 @@ void procConifg(sMCTStruct *pMCTData,sDCTStruct *pDCTData, u8 dimm, u8 pass)
 				pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5;
 			/* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization
 			   training) - RegisterDelay. */
-			/* MemClkFreq: 3: 400Mhz; 4: 533Mhz; 5: 667Mhz; 6: 800Mhz */
+			/* MemClkFreq: 3: 400MHz; 4: 533MHz; 5: 667MHz; 6: 800MHz */
 			SeedTotal = (u16) (RegisterDelay + ((((u32) SeedTotal - RegisterDelay) *
 							     freq_tab[MemClkFreq-3]) / 400));
 			Seed_Gross = (SeedTotal & 0x20) != 0 ? 1 : 2;
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 6dfb073144..7c95ab4bd2 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -196,7 +196,7 @@ static void checkDDRMax(void)
 		spd_byte0 = spd_byte1;
 	}
 
-	/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+	/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 	speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
 
 	/* current speed > max speed? */
@@ -253,14 +253,14 @@ static u8 getcasmap(u32 dimm, u16 glspeed)
 		/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
 		spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
 		if (spd_byte != 0) {
-			/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+			/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 			dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
 			if (dimm_speed >= glspeed) {
 				casmap_shift = 1; /* -.5 is a shift of 1 */
 				/* IF -1 timing is supported, check -1 timing > GeodeLink */
 				spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
 				if (spd_byte != 0) {
-					/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
+					/* Turn SPD ns time into MHz. Check what the asm does to this math. */
 					dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
 					if (dimm_speed >= glspeed) {
 						casmap_shift = 2; /* -1 is a shift of 2 */
@@ -353,7 +353,7 @@ static void set_latencies(void)
 		spd_byte0 = spd_byte1;
 	}
 
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = (spd_byte0 * memspeed) / 1000;
 	if (((spd_byte0 * memspeed) % 1000)) {
 		++spd_byte1;
@@ -373,7 +373,7 @@ static void set_latencies(void)
 		spd_byte0 = spd_byte1;
 	}
 
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
 	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
 		++spd_byte1;
@@ -393,7 +393,7 @@ static void set_latencies(void)
 		spd_byte0 = spd_byte1;
 	}
 
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
 	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
 		++spd_byte1;
@@ -413,7 +413,7 @@ static void set_latencies(void)
 		spd_byte0 = spd_byte1;
 	}
 
-	/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+	/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
 	spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
 	if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
 		++spd_byte1;
@@ -446,7 +446,7 @@ static void set_latencies(void)
 	}
 
 	if (spd_byte0) {
-		/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
+		/* (ns/(1/MHz) = (us*MHz)/1000 = clocks/1000 = clocks) */
 		spd_byte1 = (spd_byte0 * memspeed) / 1000;
 		if (((spd_byte0 * memspeed) % 1000)) {
 			++spd_byte1;
@@ -460,7 +460,7 @@ static void set_latencies(void)
 	msr.lo |= dimm_setting;
 	wrmsr(MC_CF1017_DATA, msr);
 
-	/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200Mhz mem) other wise it stay default(1) */
+	/* tWTR: Set tWTR to 2 for 400MHz and above GLBUS (200MHz mem) other wise it stay default(1) */
 	if (memspeed > 198) {
 		msr = rdmsr(MC_CF1017_DATA);
 		msr.lo &= ~(0x7 << CF1017_LOWER_WR_TO_RD_SHIFT);
@@ -672,7 +672,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
 	msr.lo &= ~(CF07_LOWER_PROG_DRAM_SET | CF07_LOWER_LOAD_MODE_DLL_RESET);
 	wrmsr(msrnum, msr);
 
-	/* 2us delay (200 clocks @ 200Mhz). We probably really don't need this but.... better safe. */
+	/* 2us delay (200 clocks @ 200MHz). We probably really don't need this but.... better safe. */
 	/* Wait 2 PORT61 ticks. between 15us and 30us */
 	/* This would be endless if the timer is stuck. */
 	while ((inb(0x61))) ;	/* find the first edge */
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index f42bef2db0..2247a256af 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -1276,7 +1276,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
 
 	/* Trd */
 
-	/* Set to a 7 clock read delay. This is for 133Mhz
+	/* Set to a 7 clock read delay. This is for 133MHz
 	 *  with a CAS latency of 2.5  if 2.0 a 6 clock
 	 *  delay is good  */
 
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index e5920df0bd..909e740131 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -1132,7 +1132,7 @@ static void configure_e7501_dram_timing(const struct mem_controller *ctrl,
 
 	/* Trd */
 
-	/* Set to a 7 clock read delay. This is for 133Mhz
+	/* Set to a 7 clock read delay. This is for 133MHz
 	 *  with a CAS latency of 2.5  if 2.0 a 6 clock
 	 *  delay is good  */
 
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 55be449636..1e335f5f13 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -439,12 +439,12 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs say use 55 for all 200Mhz */
+		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 Mhz */
+	else if(value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz
+		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
@@ -484,10 +484,10 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs state to use 99 for all 167 Mhz */
+		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 Mhz */
+	else if(value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
 		if((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 11f26ee30b..0e6e204832 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -445,12 +445,12 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs say use 55 for all 200Mhz */
+		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 Mhz */
+	else if(value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz
+		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
@@ -490,10 +490,10 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs state to use 99 for all 167 Mhz */
+		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 Mhz */
+	else if(value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
 		if((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 443972e4d6..4f5a989dc6 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -433,12 +433,12 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs say use 55 for all 200Mhz */
+		/* Docs say use 55 for all 200MHz */
 		drt |= (0x055<<24);
 	}
-	else if(value <= 0x60) { /* 167 Mhz */
+	else if(value <= 0x60) { /* 167 MHz */
 		/* according to new documentation CAS latency is 00
-		 * for bits 3:2 for all 167 Mhz
+		 * for bits 3:2 for all 167 MHz
 		drt |= ((index&3)<<2); */  /* set CAS latency */
 		if((index&0x0ff00)<=0x03000) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
@@ -478,10 +478,10 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
 		} else {
 			drt |= (2<<22);
 		}
-		/* Docs state to use 99 for all 167 Mhz */
+		/* Docs state to use 99 for all 167 MHz */
 		drt |= (0x099<<24);
 	}
-	else if(value <= 0x75) { /* 133 Mhz */
+	else if(value <= 0x75) { /* 133 MHz */
 		drt |= ((index&3)<<2);  /* set CAS latency */
 		if((index&0x0ff00)<=0x03c00) {
 			drt |= (1<<8);  /* Trp RAS Precharg */
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 26c0c4bcb5..7d283a1941 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -416,7 +416,7 @@ static void sdram_enable(void)
 	/* 0. Wait until power/voltages and clocks are stable (200us). */
 	udelay(200);
 
-	/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 Mhz). */
+	/* 1. Apply NOP. Wait 200 clock cycles (clock might be 60 or 66 MHz). */
 	PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
 	do_ram_command(RAM_COMMAND_NOP);
 	udelay(200);
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 42233e82db..e823bab455 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2028,10 +2028,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 
 	printk(BIOS_DEBUG, "Render: ");
 	switch (freq) {
-	case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
-	case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
-	case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
-	case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
+	case CRCLK_166MHz: printk(BIOS_DEBUG, "166MHz"); break;
+	case CRCLK_200MHz: printk(BIOS_DEBUG, "200MHz"); break;
+	case CRCLK_250MHz: printk(BIOS_DEBUG, "250MHz"); break;
+	case CRCLK_400MHz: printk(BIOS_DEBUG, "400MHz"); break;
 	}
 
 	if (i945_silicon_revision() == 0) {
diff --git a/src/northbridge/via/cn400/raminit.c b/src/northbridge/via/cn400/raminit.c
index 23a6209458..d15a6338e0 100644
--- a/src/northbridge/via/cn400/raminit.c
+++ b/src/northbridge/via/cn400/raminit.c
@@ -333,7 +333,7 @@ static void ddr_ram_setup(void)
 			}
 		}
 		if( b & 0x04 ){     // DDR mandatory CAS 2
-			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2
+			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max MHz at CAS 2
 				//print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -342,7 +342,7 @@ static void ddr_ram_setup(void)
 		//print_debug("\nStarting at CAS 2.5");
 		c = 0x20;          // assume CAS 2.5
 		if( b & 0x04){      // Should always happen
-			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2
+			if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max MHz at CAS 2
 				//print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
diff --git a/src/northbridge/via/vt8623/raminit.c b/src/northbridge/via/vt8623/raminit.c
index b5c78a1337..f281ce096c 100644
--- a/src/northbridge/via/vt8623/raminit.c
+++ b/src/northbridge/via/vt8623/raminit.c
@@ -21,12 +21,12 @@
 /*
   Automatically detect and set up ddr dram on the CLE266 chipset.
   Assumes DDR memory, though chipset also supports SDRAM
-  Assumes at least 266Mhz memory as no attempt is made to clock
+  Assumes at least 266MHz memory as no attempt is made to clock
   the chipset down if slower memory is installed.
   So far tested on:
-	256 Mb 266Mhz 1 Bank (i.e. single sided)
-	256 Mb 266Mhz 2 Bank (i.e. double sided)
-	512 Mb 266Mhz 2 Bank (i.e. double sided)
+	256 Mb 266MHz 1 Bank (i.e. single sided)
+	256 Mb 266MHz 2 Bank (i.e. double sided)
+	512 Mb 266MHz 2 Bank (i.e. double sided)
 */
 /* ported and enhanced from assembler level code in coreboot v1 */
 
@@ -199,13 +199,13 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 		c = 0x30;
 		/* see if we can better it */
 		if( b & 0x08 ){     // DDR mandatory CAS 2.5
-			if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
+			if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133MHz at CAS 2.5
 				print_debug("\nWe can do CAS 2.5");
 				c = 0x20;
 			}
 		}
 		if( b & 0x04 ){     // DDR mandatory CAS 2
-			if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
+			if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133MHz at CAS 2
 				print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -214,7 +214,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 		print_debug("\nStarting at CAS 2.5");
 		c = 0x20;          // assume CAS 2.5
 		if( b & 0x04){      // Should always happen
-			if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
+			if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133MHz at CAS 2
 				print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
@@ -308,7 +308,7 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 /*
     CPU Frequency  Device 0 Offset 54
 
-    CPU Frequency          54[7,6]  bootstraps at 0xc0 (133Mhz)
+    CPU Frequency          54[7,6]  bootstraps at 0xc0 (133MHz)
     DRAM burst length = 8  54[5]
 */
 	pci_write_config8(north,0x54,0xe0);
@@ -567,10 +567,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
 
     Rx69 (DRAM freq)  Rx58 (chip tech)  Rx6a
 
-    133Mhz            64/128Mb          0x86
-    133Mhz            256/512Mb         0x43
-    100Mhz            64/128Mb          0x65
-    100Mhz            256/512Mb         0x32
+    133MHz            64/128Mb          0x86
+    133MHz            256/512Mb         0x43
+    100MHz            64/128Mb          0x65
+    100MHz            256/512Mb         0x32
 */
 
 	b = pci_read_config8(north,0x58);
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index d404cde122..487dab466e 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -265,14 +265,14 @@ void SetUMARam(void)
 	outb(0x68, 0x03c4);
 	outb(VgaPortVal, 0x03c5);
 
-	//  ECLK Selection (00:166Mhz, 01:185Mhz, 10:250Mhz, 11:275Mhz)
+	//  ECLK Selection (00:166MHz, 01:185MHz, 10:250MHz, 11:275MHz)
 	// set 3C5.5A[0]=1, address maps to secondary resgiters
 	outb(0x5a, 0x03c4);
 	ByteVal = inb(0x03c5);
 	ByteVal |= 0x01;
 	outb(ByteVal, 0x03c5);
 
-	// Set 3D5.4C[7:6] (00:166Mhz, 01:185Mhz, 10:250Mhz, 11:275Mhz)
+	// Set 3D5.4C[7:6] (00:166MHz, 01:185MHz, 10:250MHz, 11:275MHz)
 	outb(0x4c, 0x03d4);
 	ByteVal = inb(0x03d5);
 	ByteVal = (ByteVal & 0x3F) | 0x80;
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index bf0b278a76..fc9a202e9b 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -334,7 +334,7 @@ static void chrome9hd_enable(device_t dev)
 {
 	device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
 				       PCI_DEVICE_ID_VIA_VX900_MEMCTRL, 0);
-	/* FIXME: here? -=- ACLK 250Mhz */
+	/* FIXME: here? -=- ACLK 250MHz */
 	pci_mod_config8(mcu, 0xbb, 0, 0x01);
 }