drop extra whitespace at end of line for i945 + ICH7 (trivial)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 15 insertions, 15 deletions

diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c
index c5ecdc5700..23aadd5752 100644
--- a/src/northbridge/intel/i945/acpi.c
+++ b/src/northbridge/intel/i945/acpi.c
@@ -1,6 +1,6 @@
 /*
  * This file is part of the coreboot project.
- * 
+ *
  * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index 49986f9cef..420ba0e592 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -29,7 +29,7 @@ Device (PDRC)
 
 	// This does not seem to work correctly yet - set values statically for
 	// now.
-	
+
 	//Name (PDRS, ResourceTemplate() {
 	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
 	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
diff --git a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
index d889b38524..9e9c43611b 100644
--- a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
@@ -26,7 +26,7 @@ Name(_CID,EISAID("PNP0A03"))	// PCI
 Device (MCHC)
 {
 	Name(_ADR, 0x00000000)	// 0:0.0
-	
+
 	OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
 	Field (MCHP, DWordAcc, NoLock, Preserve)
 	{
diff --git a/src/northbridge/intel/i945/acpi/i945_igd.asl b/src/northbridge/intel/i945/acpi/i945_igd.asl
index 806ae5dd32..a6804adb5e 100644
--- a/src/northbridge/intel/i945/acpi/i945_igd.asl
+++ b/src/northbridge/intel/i945/acpi/i945_igd.asl
@@ -101,7 +101,7 @@ Device (GFX0)
 		/* Some error happened, but we have to return something */
 		Return (Package() {0x00000400})
 	}
-	
+
 	Device(DD01)
 	{
 		/* Device Unique ID */
@@ -136,7 +136,7 @@ Device (GFX0)
 		/* Device Set State */
 		Method(_DSS, 1)
 		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
 			 * display switch was completed
 			 */
 			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
@@ -179,7 +179,7 @@ Device (GFX0)
 		/* Device Set State */
 		Method(_DSS, 1)
 		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
 			 * display switch was completed
 			 */
 			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
@@ -223,7 +223,7 @@ Device (GFX0)
 		/* Device Set State */
 		Method(_DSS, 1)
 		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
 			 * display switch was completed
 			 */
 			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
@@ -267,7 +267,7 @@ Device (GFX0)
 		/* Device Set State */
 		Method(_DSS, 1)
 		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
 			 * display switch was completed
 			 */
 			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
@@ -311,7 +311,7 @@ Device (GFX0)
 		/* Device Set State */
 		Method(_DSS, 1)
 		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
 			 * display switch was completed
 			 */
 			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index 7e1049c084..a43ef259aa 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -39,7 +39,7 @@ static void gma_func1_init(struct device *dev)
 
 	/* IGD needs to be Bus Master, also enable IO accesss */
 	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 | 
+	pci_write_config32(dev, PCI_COMMAND, reg32 |
 			PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 }
 
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index f7f0ed7b77..a1f7185bde 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -290,7 +290,7 @@
 
 #define PORTARB		0x100	/* 256bit */
 
-/* 
+/*
  * DMIBAR
  */
 
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 73b29abddf..5bc1025c4c 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -43,7 +43,7 @@ int get_pcie_bar(u32 *base, u32 *len)
 	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!dev)
 		return 0;
-	
+
 	pciexbar_reg = pci_read_config32(dev, 0x48);
 
 	if (!(pciexbar_reg & (1 << 0)))
@@ -78,12 +78,12 @@ int add_northbridge_resources(struct lb_memory *mem)
 	u32 pcie_config_base, pcie_config_size;
 
 	printk_debug("Adding UMA memory area\n");
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 
 	printk_debug("Adding PCIe config bar\n");
 	get_pcie_bar(&pcie_config_base, &pcie_config_size);
-	lb_add_memory_range(mem, LB_MEM_RESERVED, 
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		pcie_config_base, pcie_config_size);
 
 	return 0;
diff --git a/src/northbridge/intel/i945/reset_test.c b/src/northbridge/intel/i945/reset_test.c
index 80d6316d1a..6e5c5274e9 100644
--- a/src/northbridge/intel/i945/reset_test.c
+++ b/src/northbridge/intel/i945/reset_test.c
@@ -19,7 +19,7 @@
 
 static int bios_reset_detected(void)
 {
-	/* For now ... 
+	/* For now ...
 	 * DO NOT, I repeat, DO NOT remove this. If you don't like the
 	 * situation, implement this instead.
 	 */