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| author | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-18 20:42:58 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2006-04-18 20:42:58 +0000 |
| commit | 170ce333ca2d18df9ad1237dc9ac14e5ce235266 (patch) | |
| tree | 26735f4edc25723e99ef0ec9e72f3ac7b0e14f02 /src/northbridge | |
| parent | df46cb205d57a91aa0fff142b2dd951e7731731b (diff) | |
| download | coreboot-170ce333ca2d18df9ad1237dc9ac14e5ce235266.tar.xz | |
add ram resources
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/gx2/northbridge.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index 7c3cb52623..981d5375e1 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -236,10 +236,11 @@ setup_gx2(void) static void optimize_xbus(device_t dev) { /* Optimise X-Bus performance */ - pci_write_config8(dev, 0x40, 0x1e); +/* pci_write_config8(dev, 0x40, 0x1e); pci_write_config8(dev, 0x41, 0x52); pci_write_config8(dev, 0x43, 0xc1); pci_write_config8(dev, 0x44, 0x00); +*/ } static void enable_shadow(device_t dev) @@ -433,6 +434,7 @@ static void enable_dev(struct device *dev) do_vsmbios(); dev->ops = &pci_domain_ops; pci_set_method(dev); + ram_resource(dev, 0, 0, sizeram()*1024); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { printk_debug("DEVICE_PATH_APIC_CLUSTER\n"); |