Improving BKDG implementation of P-states,

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it for good mesure.

If I understood BKDG fam10 CPUs never need a software initiated vid transition,
because the hardware knows what to do when you just request
a Pstate change if the cpu is properly configured. In fact
unifying a little what PVI and SVI do was better for my board (SVI).
So I drop transitionVid, which I didn't understand either (why
did it have a case for PVI if it is never called for PVI ?
Why did the PVI case distinguigh cpu or nb when PVI is
theoretically single voltage plane ? ).

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 20 insertions, 8 deletions

diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h
index 0f6db9fc75..4c327e971c 100644
--- a/src/northbridge/amd/amdht/AsPsDefs.h
+++ b/src/northbridge/amd/amdht/AsPsDefs.h
@@ -231,6 +231,16 @@
 
 /* F3x1FC Product Information Register */
 #define NB_COF_VID_UPDATE_MASK 1 /* for CPU rev <= C */
+#define SINGLE_PLANE_NB_FID_MASK 0x007c/* for CPU rev <= C */
+#define SINGLE_PLANE_NB_FID_SHIFT 2/* for CPU rev <= C */
+#define SINGLE_PLANE_NB_VID_MASK 0x3f80/* for CPU rev <= C */
+#define SINGLE_PLANE_NB_VID_SHIFT 7/* for CPU rev <= C */
+
+#define DUAL_PLANE_NB_FID_OFF_MASK 0x001c000/* for CPU rev <= C */
+#define DUAL_PLANE_NB_FID_SHIFT 14/* for CPU rev <= C */
+#define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */
+#define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */
+
 
 #define NM_PS_REG 5			/* number of P-state MSR registers */
 
@@ -266,4 +276,9 @@
 #define GH_REV_A2 0x4			/* GH Rev A2 logical ID, Upper half */
 
 
+#define TSC_MSR 0x10
+#define CUR_PSTATE_MSR 0xc0010063
+
+#define  WAIT_PSTATE_TIMEOUT 80000000  /* 0.1 s , unit : 1.25 ns */
+
 #endif
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 0ef60acecd..584a220864 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -339,9 +339,6 @@ static void mctHookAfterDramInit(void)
 {
 }
 
-static void coreDelay (void);
-
-
 #if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
 /* Erratum 350 */
 static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat)
@@ -408,10 +405,10 @@ static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTs
 static void vErratum372(struct DCTStatStruc *pDCTstat)
 {
         msr_t msr = rdmsr(NB_CFG_MSR);
-  
+
         int  nbPstate1supported = ! (msr.hi && (1 << (NB_GfxNbPstateDis -32))) ;
 
-        // is this the right way to check for NB pstate 1 or DDR3-1333 ? 
+        // is this the right way to check for NB pstate 1 or DDR3-1333 ?
         if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
             &&(!pDCTstat->GangedMode)) {
            	/* DisableCf8ExtCfg */
@@ -423,14 +420,14 @@ static void vErratum372(struct DCTStatStruc *pDCTstat)
 static void vErratum414(struct DCTStatStruc *pDCTstat)
 {
      int dct=0;
-    for(; dct < 2 ; dct++) 
+    for(; dct < 2 ; dct++)
     {
-        int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct)); 
+        int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
         int powerDown =  dRAMConfigHi && (1 << PowerDownEn ) ;
         int ddr3 = dRAMConfigHi && (1 << Ddr3Mode ) ;
         int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
         int pchgPDModeSel = dRAMMRS && (1 << PchgPDModeSel ) ;
-	if (powerDown && ddr3 && pchgPDModeSel ) 
+	if (powerDown && ddr3 && pchgPDModeSel )
 	{
 	  Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
 	}