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authorArthur Heymans <arthur@aheymans.xyz>2019-11-11 20:18:24 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-14 11:30:34 +0000
commit2452afbe04584d48a9d76535f943c0cfc641aa19 (patch)
tree0ce5aed52511660ab274d8a0aeb95cb606a7b57a /src/northbridge
parentaa990e928910e35edb115095898c4668becdf1d8 (diff)
downloadcoreboot-2452afbe04584d48a9d76535f943c0cfc641aa19.tar.xz
mb/*/*(ich7/x4x): Use common early southbridge init
One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/x4x/early_init.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c
index d48b8f0263..f89411e482 100644
--- a/src/northbridge/intel/x4x/early_init.c
+++ b/src/northbridge/intel/x4x/early_init.c
@@ -41,12 +41,6 @@ void x4x_early_init(void)
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
- /* Setup PMBASE */
- if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) {
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x80);
- }
-
/* Setup HECIBAR */
pci_write_config32(PCI_DEV(0, 3, 0), 0x10, DEFAULT_HECIBAR);
@@ -59,15 +53,6 @@ void x4x_early_init(void)
pci_write_config8(d0f0, D0F0_PAM(5), 0x33);
pci_write_config8(d0f0, D0F0_PAM(6), 0x33);
- if (!CONFIG(SOUTHBRIDGE_INTEL_I82801JX)) {
- printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
- RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
- outw(1 << 11, DEFAULT_PMBASE + 0x60 + 0x08); /* halt timer */
- outw(1 << 3, DEFAULT_PMBASE + 0x60 + 0x04); /* clear timeout */
- outw(1 << 1, DEFAULT_PMBASE + 0x60 + 0x06); /* clear 2nd timeout */
- printk(BIOS_DEBUG, " done.\n");
- }
-
if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) {
/* Enable internal GFX */
pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN);