intel: Correct MMIO related ACPI table settings

Several of the intel platforms define the region reserved
for PCI memory resources in a location where it overlaps
with the MMIO (MCFG) region.

Using the memory map from mohon_peak as an example:

  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1. 0000000000001000-000000000009ffff: RAM
  2. 00000000000a0000-00000000000fffff: RESERVED
  3. 0000000000100000-000000007fbcffff: RAM
  4. 000000007fbd0000-000000007fbfffff: CONFIGURATION TABLES
  5. 000000007fc00000-000000007fdfffff: RESERVED
  6. 00000000e0000000-00000000efffffff: RESERVED
  7. 00000000fee00000-00000000fee00fff: RESERVED
  8. 0000000100000000-000000017fffffff: RAM

  The ACPI table describing the space set aside for PCI memory
  (not to be confused with the MMIO config space) is defined
  as the region from BMBOUND (the top of DRAM below 4GB) to
  a hardcoded value of 0xfebfffff. That region would overlap
  the MMIO region at 0xe0000000-0xefffffff. For rangeley
  the upper bound of the PCI memory space should be set
  to 0xe0000000 - 1.

  The MCFG regions for several of the affected chipsets are:
  rangeley    0xe0000000-0xefffffff
  baytrail    0xe0000000-0xefffffff
  haswell     0xf0000000-0xf3ffffff
  sandybridge 0xf8000000-0xfbffffff

TEST = intel/mohonpeak and intel/bayleybay.

Change-Id: Ic188a4f575494f04930dea4d0aaaeaad95df9f90
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/9972
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)

4 files changed, 18 insertions, 13 deletions

diff --git a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
index 5cefaeb939..44108150d3 100644
--- a/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
+++ b/src/northbridge/intel/fsp_rangeley/acpi/hostbridge.asl
@@ -111,11 +111,11 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 				0x00010000,,, FSEG)
 
-		// PCI Memory Region (Top of memory-0xfebfffff)
+		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
-				0xfec00000,,, PM01)
+				0x00000000, 0x00000000, 0, 0x00000000,
+				0,,, PM01)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -131,7 +131,9 @@ Method (_CRS, 0, Serialized)
 
 	// Fix up PCI memory region
 	// Start with Top of Lower Usable DRAM
-	Store (BMBD, PMIN)					// Memory goes from BMBOUND to 0xfebfffff (PM01 above)
+	// Memory goes from BMBOUND to CONFIG_MMCONF_BASE_ADDRESS (PM01 above)
+	Store (BMBD, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add(Subtract(PMAX, PMIN), 1, PLEN)	// Store Memory Size
 
 	Return (MCRS)
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
index e82758c494..ea0967926e 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
@@ -320,11 +320,11 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 				0x00010000,,, FSEG)
 
-		// PCI Memory Region (Top of memory-0xfebfffff)
+		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
-				0xfec00000,,, PM01)
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000,,, PM01)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -350,6 +350,7 @@ Method (_CRS, 0, Serialized)
 	}
 
 	Store (Local0, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add(Subtract(PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 9bc5549041..44743672b3 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -426,11 +426,11 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 				0x00010000,,, FSEG)
 
-		// PCI Memory Region (Top of memory-0xfebfffff)
+		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
-				0xfec00000,,, PM01)
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000,,, PM01)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -456,6 +456,7 @@ Method (_CRS, 0, Serialized)
 	}
 
 	Store (Local0, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add(Subtract(PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 26f7514646..f2720cfb19 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -344,11 +344,11 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
 				0x00010000,,, FSEG)
 
-		// PCI Memory Region (Top of memory-0xfebfffff)
+		// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
-				0xfec00000,,, PM01)
+				0x00000000, 0x00000000, 0x00000000, 0x00000000,
+				0x00000000,,, PM01)
 
 		// TPM Area (0xfed40000-0xfed44fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -374,6 +374,7 @@ Method (_CRS, 0, Serialized)
 	}
 
 	Store (Local0, PMIN)
+	Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
 	Add(Subtract(PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)