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authorIru Cai <mytbk920423@gmail.com>2019-06-11 14:24:43 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-07-29 05:59:52 +0000
commit336420348eed277f8640fc9c19aa463c2848650d (patch)
tree5d3d607d08a5e8580d5493b6e5798db320a68f7a /src/northbridge
parentb85ddc5d44cb76fa3dbec461c949fb79b66decec (diff)
downloadcoreboot-336420348eed277f8640fc9c19aa463c2848650d.tar.xz
haswell: reinitialize EHCI debug hardware after raminit
Tested on Lenovo ThinkPad T440p. Change-Id: I54b0c9dbb64819f0f502783b632470d27ed0b2b1 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34358 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/haswell/raminit.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c
index 9beb23cc8e..2fdbe07c8d 100644
--- a/src/northbridge/intel/haswell/raminit.c
+++ b/src/northbridge/intel/haswell/raminit.c
@@ -14,6 +14,7 @@
*/
#include <console/console.h>
+#include <console/usb.h>
#include <string.h>
#include <cbmem.h>
#include <arch/cbfs.h>
@@ -155,6 +156,11 @@ void sdram_initialize(struct pei_data *pei_data)
asm volatile (
"call *%%ecx\n\t"
:"=a" (rv) : "c" (entry), "a" (pei_data));
+
+ /* mrc.bin reconfigures USB, so reinit it to have debug */
+ if (CONFIG(USBDEBUG_IN_PRE_RAM))
+ usbdebug_hw_init(true);
+
if (rv) {
switch (rv) {
case -1: