janitor task: unify and cleanup naming.

cache_as_ram_auto.c and auto.c are both called "romstage.c" now.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 9 insertions, 9 deletions

diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index b0aee4bccc..bb0f865a00 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -18,7 +18,7 @@
  */
 
 /*
- * Generic FAM10 debug code, used by mainboard specific car_auto.c
+ * Generic FAM10 debug code, used by mainboard specific romstage.c
  */
 
 #include "amdfam10_pci.c"
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 55e232f95a..f9e9671a3e 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -1,5 +1,5 @@
 /*
- * generic K8 debug code, used by mainboard specific auto.c
+ * generic K8 debug code, used by mainboard specific romstage.c
  *
  */
 
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index e97930e978..75ed33ea40 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -1,5 +1,5 @@
 /*
- * generic debug code, used by mainboard specific auto.c
+ * generic debug code, used by mainboard specific romstage.c
  *
  */
 #if 1
diff --git a/src/northbridge/intel/i855gme/debug.c b/src/northbridge/intel/i855gme/debug.c
index 46d629b01e..4083add6f1 100644
--- a/src/northbridge/intel/i855gme/debug.c
+++ b/src/northbridge/intel/i855gme/debug.c
@@ -19,7 +19,7 @@
  */
 
 /*
- * generic K8 debug code, used by mainboard specific auto.c
+ * generic K8 debug code, used by mainboard specific romstage.c
  *
  */
 #if 1
diff --git a/src/northbridge/intel/i855pm/debug.c b/src/northbridge/intel/i855pm/debug.c
index 67670f9844..7b854455a9 100644
--- a/src/northbridge/intel/i855pm/debug.c
+++ b/src/northbridge/intel/i855pm/debug.c
@@ -1,5 +1,5 @@
 /*
- * generic K8 debug code, used by mainboard specific auto.c
+ * generic K8 debug code, used by mainboard specific romstage.c
  *
  */
 #if 1
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 4083cef2c1..124ef147c3 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -2796,7 +2796,7 @@ static void sdram_enable_memory_clocks(struct sys_info *sysinfo)
 	 * signals to be disabled.
 	 * If other similar mainboard occur, it would make sense to make
 	 * this an entry in the sysinfo structure, and pre-initialize that
-	 * structure in the mainboard's auto.c main() function.
+	 * structure in the mainboard's romstage.c main() function.
 	 * For now an #ifdef will do.
 	 */
 
diff --git a/src/northbridge/via/cx700/cx700_early_smbus.c b/src/northbridge/via/cx700/cx700_early_smbus.c
index 218ae0a7a1..ed79744db4 100644
--- a/src/northbridge/via/cx700/cx700_early_smbus.c
+++ b/src/northbridge/via/cx700/cx700_early_smbus.c
@@ -188,7 +188,7 @@ static unsigned int get_spd_data(const struct mem_controller *ctrl, unsigned int
 	smbus_wait_until_ready();
 
 	/* Fetch the SMBus address of the SPD ROM from
-	 * the ctrl struct in auto.c in case they are at
+	 * the ctrl struct in romstage.c in case they are at
 	 * non-standard positions.
 	 * SMBus Address shifted by 1
 	 */
diff --git a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c b/src/northbridge/via/vx800/examples/romstage.c
index fa8962b168..c1de3f3dc2 100644
--- a/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
+++ b/src/northbridge/via/vx800/examples/romstage.c
@@ -559,13 +559,13 @@ g)      Rx73h = 32h
 	}
 #endif
 /*
-the following code is  copied from src\mainboard\tyan\s2735\cache_as_ram_auto.c
+the following code is  copied from src/mainboard/tyan/s2735/romstage.c
 Only the code around CLEAR_FIRST_1M_RAM is changed.
 I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c"
 the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, 
 and cpu/x86/car/cache_as_ram_post.c  do not cache my $CONFIG_XIP_ROM_BASE+SIZE area.
 
-So,I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff withx86-version
+So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff with x86-version
 */
 #if 1
 	{