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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-12-03 14:06:02 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-13 08:58:12 +0000 |
| commit | 3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09 (patch) | |
| tree | 98196a78b5aed35d8c238cfb6b86668506e526e5 /src/northbridge | |
| parent | 24f0455016720e4222057ecda3415c05c7cb095c (diff) | |
| download | coreboot-3d5e1e5d52b83306bcc8a32fc26f89d7f25bbb09.tar.xz | |
sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock,
this call can be delayed to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/amd/agesa/family14/state_machine.c | 18 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/state_machine.h | 1 |
2 files changed, 12 insertions, 7 deletions
diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index df55efa749..91a8f70259 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -29,24 +29,30 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { + if (!boot_cpu()) + return; + + if (!CONFIG(ROMCC_BOOTBLOCK)) + sb_Poweron_Init(); + /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * would fail later in AmdInitPost(), when DRAM is already configured * and C6DramLock bit has been set. * * As a workaround, do a hard reset to clear C6DramLock bit. */ + #ifdef __SIMPLE_DEVICE__ pci_devfn_t dev = PCI_DEV(0, 0x18, 2); #else struct device *dev = pcidev_on_root(0x18, 2); #endif - if (boot_cpu()) { - u32 mct_cfg_lo = pci_read_config32(dev, 0x118); - if (mct_cfg_lo & (1<<19)) { - printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); - system_reset(); - } + u32 mct_cfg_lo = pci_read_config32(dev, 0x118); + if (mct_cfg_lo & (1<<19)) { + printk(BIOS_CRIT, "C6DramLock is set, resetting\n"); + system_reset(); } + } void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 9de011a062..c4a30540b5 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -45,7 +45,6 @@ struct sysinfo }; void board_BeforeAgesa(struct sysinfo *cb); -void platform_once(struct sysinfo *cb); void agesa_set_interface(struct sysinfo *cb); |