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| author | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-05 19:46:45 +0100 |
|---|---|---|
| committer | Vladimir Serbinenko <phcoder@gmail.com> | 2014-02-25 00:57:35 +0100 |
| commit | 4337020b950454815204eed4e43a894be0b125ca (patch) | |
| tree | 7aa3a4ad420a54b3079f3216d577aafab1bca2e0 /src/northbridge | |
| parent | 20f83d56561879045ecade24d51e79dfb151baf6 (diff) | |
| download | coreboot-4337020b950454815204eed4e43a894be0b125ca.tar.xz | |
Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.
CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency
Remove this as a buggy feature until we figure out how to do it properly
if necessary.
Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/fsp_sandybridge/Kconfig | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 2 |
3 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 0c3d5f5156..ce366ef1ba 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -87,14 +87,10 @@ config CBFS_SIZE config ENABLE_FAST_BOOT bool "Enable Fast Boot" default y if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X - depends on !CACHE_ROM help Enabling this feature will cause MRC data to be cached in NV storage which will speed up boot time on future reboots and/or power cycles. - WARNING: This feature combined with the CACHE_ROM may result in undefined - behavior. - config MRC_CACHE_SIZE hex "MRC Data Cache Size" default 0x10000 diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index f9386dedcc..d94bc09ba8 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -340,8 +340,6 @@ static const struct pci_driver mc_driver_44 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 7db9301c30..5440140089 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -476,8 +476,6 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); - /* Enable ROM caching if option was selected. */ - x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) |