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| author | Nico Huber <nico.h@gmx.de> | 2017-07-16 16:40:41 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-10-28 19:46:17 +0000 |
| commit | 504d1eff4bd324915f5c44223ab03086b0cbbd2c (patch) | |
| tree | bde35bdf0c7bd59456af336735c4e5c69bfc71ae /src/northbridge | |
| parent | 18228168a5e5ada33390ca96ef4b6ee80a509a89 (diff) | |
| download | coreboot-504d1eff4bd324915f5c44223ab03086b0cbbd2c.tar.xz | |
3rdparty/lib{hwbase,gfxinit}: Update to latest master
Simplifies our C interface function gma_gfxinit(), due to the following
changes:
* *libgfxinit* knows about the underlying PCI device now and can
probe MMIO addresses by itself.
* The framebuffer mapping is now completely handled inside the
library where we validate that we neither overflow
- the stolen memory,
- the GTT address space, the GTT itself nor
- the aperture window (i.e. resource2 of the PCI device)
that we use to access the framebuffer.
Other changes:
* Fixes and a quirk for DP training.
* Fix for DP-VGA adapters that report an analog display in EDID.
* Fixes for Skylake support with coreboot.
* DDI Buffer drive-strength configuration for Haswell, Broadwell and
Skylake.
* `gfx_test` can now be run from X windows (with glitches).
* Compatibility with GCC 7 and SPARK GPL 2017.
TEST=Booted lenovo/t420 and verified that everything works as usual.
Change-Id: I001ba973d864811503410579fd7ad55ab8612759
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge')
| -rw-r--r-- | src/northbridge/intel/haswell/gma.c | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/gma.c | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/gma.c | 3 |
3 files changed, 3 insertions, 13 deletions
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 535a7f0af0..c7319fbec8 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -456,12 +456,6 @@ static void gma_func0_init(struct device *dev) { int lightup_ok = 0; u32 reg32; - u64 physbase; - const struct resource *const linearfb_res = - find_resource(dev, PCI_BASE_ADDRESS_2); - - if (!linearfb_res || !linearfb_res->base) - return; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -476,9 +470,7 @@ static void gma_func0_init(struct device *dev) if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - gma_gfxinit(gtt_res->base, linearfb_res->base, - physbase, &lightup_ok); + gma_gfxinit(&lightup_ok); gfx_set_init_done(1); } diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 591a2d6f56..0db8f3c88a 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -1061,8 +1061,7 @@ static void gma_func0_init(struct device *dev) gtt_res->base); if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { int lightup_ok; - gma_gfxinit(gtt_res->base, lfb_res->base, - physbase, &lightup_ok); + gma_gfxinit(&lightup_ok); } else { intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base); diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 4cda965f4e..61b9008467 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -648,8 +648,7 @@ static void gma_func0_init(struct device *dev) int lightup_ok; if (IS_ENABLED(CONFIG_MAINBOARD_USE_LIBGFXINIT)) { - gma_gfxinit((uintptr_t)mmiobase, graphics_base, - physbase, &lightup_ok); + gma_gfxinit(&lightup_ok); } else { lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base); |