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authorPhilipp Deppenwiese <zaolin@das-labor.org>2017-10-18 17:13:07 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-01-18 01:35:31 +0000
commit64e2d19082636de9e82674ccfca574269bb34712 (patch)
treedfe44c9b1cebbb611b99474c1ee096e23f930796 /src/northbridge
parent4fef7818ecd002e5971ea6287e402fd9276b7266 (diff)
downloadcoreboot-64e2d19082636de9e82674ccfca574269bb34712.tar.xz
security/tpm: Move tpm TSS and TSPI layer to security section
* Move code from src/lib and src/include into src/security/tpm * Split TPM TSS 1.2 and 2.0 * Fix header includes * Add a new directory structure with kconfig and makefile includes Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/intel/sandybridge/romstage.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c
index 8608d5a8a4..1f31ad611e 100644
--- a/src/northbridge/intel/sandybridge/romstage.c
+++ b/src/northbridge/intel/sandybridge/romstage.c
@@ -28,7 +28,7 @@
#include <device/pci_def.h>
#include <device/device.h>
#include <halt.h>
-#include <tpm.h>
+#include <security/tpm/tpm.h>
#include <northbridge/intel/sandybridge/chip.h>
#include "southbridge/intel/bd82x6x/pch.h"
#include <southbridge/intel/common/gpio.h>